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    Electronic package with filled blind vias
    45.
    发明申请
    Electronic package with filled blind vias 有权
    带盲孔的电子封装

    公开(公告)号：US20040132279A1

    公开(公告)日：2004-07-08

    申请号：US10729174

    申请日：2003-12-05

    Applicant: International Business Machines Corporation

    Inventor： Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

    IPC: H01L021/4763 ,  H01L021/44

    CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00

    Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

    Abstract translation: 通过在层叠到用作接地平面或电源平面的导电金属芯的第一电介质层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。 通过延伸到芯的电介质层提供孔。 使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。 金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。 第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。 该第二通孔可以由常规电镀技术形成。 可以以这种方式组装具有堆叠的盲孔的多个电介质层。

    Multi-layer circuit assembly and process for preparing the same
    48.
    发明授权
    Multi-layer circuit assembly and process for preparing the same 失效
    多层电路组装及其制备方法

    公开(公告)号：US06671950B2

    公开(公告)日：2004-01-06

    申请号：US09901373

    申请日：2001-07-09

    Applicant: Lance C. Sturni ,  Kevin C. Olson

    Inventor： Lance C. Sturni ,  Kevin C. Olson

    IPC: H01K310

    CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.

    Abstract translation: 提供一种制造多层电路组件的方法，包括以下步骤：（a）提供具有500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的通孔密度的穿孔导电芯;（b ）在所述导电芯的所有暴露表面上施加电介质涂层以在所述导电芯的所有暴露表面上形成共形涂层;（c）以预定图案烧蚀所述电介质涂层的表面以暴露所述导电芯部分 芯;（d）将金属层施加到所有表面以通过导电芯形成金属化通孔; 另外还可以包括诸如电路化的其它处理步骤。还提供了通过本发明的方法生产的多层电路组件，其包括具有高通孔密度和热量的组分层 与可以作为电路组件的组件附接的半导体芯片和刚性线路板的扩展系数相容。

    Multi-layer integrated circuit package
    50.
    发明申请
    Multi-layer integrated circuit package 失效
    多层集成电路封装

    公开(公告)号：US20030184987A1

    公开(公告)日：2003-10-02

    申请号：US10109792

    申请日：2002-03-29

    Inventor： Boyd L. Coomer ,  Michael Walk

    IPC: H05K001/11 ,  H05K003/36 ,  H05K003/20

    CPC classification number: H01L21/4857 ,  H05K3/107 ,  H05K3/386 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T29/49126 ,  Y10T29/49128

    Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

    Abstract translation: 将粘合材料施加到金属芯层的表面。 从金属芯层的导电区域去除粘合剂材料。 金属接触件设置在金属芯层的导电区域上。 金属芯层层压到压印堆积层上，积层层具有电介质区域和导电区域，其中金属芯层的非导电区域结合到堆积层的电介质区域和金属芯层的导电区域 芯层结合到印迹堆积层的导电区域。

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