公开(公告)号：US20140208590A1

公开(公告)日：2014-07-31

申请号：US13754799

申请日：2013-01-30

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ronilo V. Boja ,  Abraham Fong Yee ,  Zuhair Bokharey

IPC: H05K3/00

CPC classification number: H05K3/0094 ,  H05K3/0032 ,  H05K3/0047 ,  H05K3/42 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49165

Abstract: A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

Abstract translation: 公开了一种用于制造在厚衬底中形成的具有高密度微孔的印刷电路板的方法。 该方法包括以下步骤：使用激光钻孔技术在厚基底中形成一个或多个孔，用导电材料电镀一个或多个孔，其中导电材料不完全填充一个或多个孔，并填充一个 或更多的电镀孔与非导电材料。

公开(公告)号：US08735741B2

公开(公告)日：2014-05-27

申请号：US13301152

申请日：2011-11-21

Applicant: Masaaki Harazono ,  Yoshihiro Hosoi

Inventor： Masaaki Harazono ,  Yoshihiro Hosoi

IPC: H05H1/11 ,  H05K1/03

CPC classification number: H05K1/0366 ,  H01L2224/16225 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/42 ,  H05K2201/0209 ,  H05K2201/0959

Abstract: A circuit board comprises a substrate; a through hole penetrating the substrate along with a direction of a thickness thereof; and a through hole conductor covering an inner wall of the through hole. The substrate comprises a first fiber layer, a second fiber layer, and a resin layer arranged between the first fiber layer and the second fiber layer. Each of the first fiber layer and the second fiber layer has a plurality of fibers and a resin arranged among the plurality of the fibers. The resin layer contains a resin and doesn't contain a fiber. The inner wall of the through hole, in a cross-section view along with the direction of the thickness of the substrate, comprises a curved depression in the resin layer.

Abstract translation: 电路板包括基板; 贯穿基板的通孔及其厚度方向; 以及覆盖通孔的内壁的通孔导体。 基板包括第一纤维层，第二纤维层和布置在第一纤维层和第二纤维层之间的树脂层。 第一纤维层和第二纤维层中的每一个具有布置在多个纤维中的多个纤维和树脂。 树脂层含有树脂，不含纤维。 贯穿孔的内壁与基板的厚度方向一起在横截面图中包括树脂层中的弯曲凹陷。

公开(公告)号：US08604345B2

公开(公告)日：2013-12-10

申请号：US13354446

申请日：2012-01-20

Applicant: Seok Hwan Ahn ,  Young Gwan Ko

Inventor： Seok Hwan Ahn ,  Young Gwan Ko

IPC: H05K1/00

CPC classification number: H05K3/107 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/1461

Abstract: A printed circuit board having a plating pattern buried in a via. The printed circuit board has: an insulating substrate including an electrically insulating resin; a via hole passing through the insulating substrate; a via including a metal layer formed on an inner wall of the via hole and a filler charged in the via hole; a circuit layer including a circuit pattern buried in the insulating substrate and transmitting an electrical signal; and a plating pattern buried in an end of the filler.

Abstract translation: 具有掩埋在通孔中的电镀图案的印刷电路板。 印刷电路板具有：包含电绝缘树脂的绝缘基板; 穿过所述绝缘基板的通孔; 通孔，其包括形成在所述通孔的内壁上的金属层和填充在所述通孔中的填充物; 电路层，其包括埋在所述绝缘基板中并传输电信号的电路图案; 以及埋在填料末端的电镀图案。

公开(公告)号：US20130319734A1

公开(公告)日：2013-12-05

申请号：US13595900

申请日：2012-08-27

Applicant: Sang Hyun Shin ,  Kwang Jik Lee ,  Hye Sook Shin ,  Joon Seok Kang

Inventor： Sang Hyun Shin ,  Kwang Jik Lee ,  Hye Sook Shin ,  Joon Seok Kang

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/03

CPC classification number: H01L21/486 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/424 ,  H05K3/427 ,  H05K3/445 ,  H05K2201/0959 ,  H05K2203/0716 ,  H05K2203/1423 ,  H01L2924/00

Abstract: Disclosed herein is a package substrate including: a base substrate; insulation layers formed on upper and lower portions of the base substrate; a first metal layer formed on an upper portion of the insulation layer; a first through-via penetrating through the base substrate, the insulation layer, and the first metal layer and being made of an insulating material; a seed layer formed on upper and lower portions and an inner wall of the first through-via; a second metal layer formed on upper portions of the first metal layer and the seed layer; and a second through-via formed in the seed layer formed at the inner wall of the first through-via and the second metal layer.

Abstract translation: 本文公开了一种封装衬底，包括：基底; 形成在基底基板的上部和下部的绝缘层; 形成在所述绝缘层的上部的第一金属层; 穿过基底基板，绝缘层和第一金属层并由绝缘材料制成的第一通孔; 形成在第一通孔的上部和下部以及内壁上的种子层; 形成在第一金属层和种子层的上部的第二金属层; 以及形成在形成在第一通孔和第二金属层的内壁处的种子层中的第二通孔。

公开(公告)号：US08592688B2

公开(公告)日：2013-11-26

申请号：US12649038

申请日：2009-12-29

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/16

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

公开(公告)号：US08580066B2

公开(公告)日：2013-11-12

申请号：US13372088

申请日：2012-02-13

Applicant: Erina Yamada ,  Hironori Sato

Inventor： Erina Yamada ,  Hironori Sato

IPC: B29C65/52 ,  B32B37/02 ,  B32B37/12 ,  B32B38/10 ,  B32B38/04 ,  B32B43/00 ,  C09J5/00

CPC classification number: H05K3/4682 ,  H01L2924/15174 ,  H05K3/0097 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/1536 ,  Y10T156/1056

Abstract: A method for manufacturing a reliable multilayer wiring substrate at a relatively low cost having little or no warpage or distortion is provided. In certain embodiments an insulation core made of an insulation material that is more rigid than that of resin insulation layers is prepared. A through hole is formed through core upper and lower surfaces of the insulation core, and a through hole conductor is formed therein. A plate-like substrate is prepared, and resin insulation layers and at least one conductor layer are laminated on the substrate to form a first buildup layer. The insulation core is laminated on the first buildup layer so as to electrically connect the conductor layer and the through hole conductor. Resin insulation layers and at least one conductor layer are then laminated on the insulation core. Lastly, the substrate is separated from the first buildup layer to yield a multilayer wiring substrate.

Abstract translation: 提供了具有很少或没有翘曲或变形的成本较低的可靠的多层布线基板的制造方法。 在某些实施例中，制备由绝缘材料制成的绝缘芯，该绝缘芯比树脂绝缘层更硬。 通过绝缘芯的中心和下表面形成通孔，并在其中形成通孔导体。 制备板状基板，在基板上层叠树脂绝缘层和至少一层导体层，形成第一累积层。 绝缘芯层压在第一堆积层上，以电连接导体层和通孔导体。 树脂绝缘层和至少一个导体层然后层压在绝缘芯上。 最后，将基板与第一堆积层分离，得到多层布线基板。

公开(公告)号：US20130249112A1

公开(公告)日：2013-09-26

申请号：US13897202

申请日：2013-05-17

Applicant: Todd B. Myers ,  Nicolas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicolas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US20130248234A1

公开(公告)日：2013-09-26

申请号：US13872650

申请日：2013-04-29

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/18

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US08528202B2

公开(公告)日：2013-09-10

申请号：US11513478

申请日：2005-02-17

Applicant: Tetsuo Yumoto

Inventor： Tetsuo Yumoto

IPC: H05K3/42

CPC classification number: G01R31/28 ,  H05K1/0284 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09236 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165 ,  Y10T29/49176

Abstract: A molding pin for a metal die is prevented from breaking, solder is surely deposited, and thus, a circuit pitch can be reduced to the limit. On the front plane of a circuit board, prescribed circuit patterns made of a conductive material are formed, and on the rear plane, prescribed circuit patterns are also formed. On the circuit board, a through hole is formed to carry electricity between the circuit patterns on both planes. The inner shape of the through hole is narrow in a direction between the adjacent circuit patterns and wide in a circuit extending direction.

Abstract translation: 防止金属模具的成型销断裂，确实沉积焊料，因此可以将电路间距减小到极限。 在电路板的正面上，形成由导电材料制成的规定的电路图案，在背面也形成规定的电路图形。 在电路板上，形成通孔，以在两个平面上的电路图案之间承载电力。 通孔的内部形状在相邻电路图案之间的方向上窄，并且在电路延伸方向上宽。

公开(公告)号：US08499446B2

公开(公告)日：2013-08-06

申请号：US13187060

申请日：2011-07-20

Applicant: Toru Nakai ,  Sho Akai

Inventor： Toru Nakai ,  Sho Akai

IPC: H05K3/02 ,  C25D5/02

CPC classification number: H05K3/4644 ,  H05K3/108 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/073 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract translation: 一种制造多层印刷线路板的方法包括在第一层间树脂绝缘层上形成第一层间树脂绝缘层，第一导体电路，第二层间树脂绝缘层，第二层间树脂绝缘层中的开口部分，露出面 第一导体电路的第二层间树脂绝缘层上的无电镀膜和暴露面，以及化学镀膜上的电镀抗蚀剂。 该方法还包括用具有比无电镀膜低的离子倾向的薄膜导体层和暴露面的金属代替化学镀膜，在化学镀膜的一部分上形成包括金属的电镀膜 和薄膜导体层，剥离电镀抗蚀剂，以及除去通过剥离暴露的化学镀膜。