公开(公告)号：US20090159326A1

公开(公告)日：2009-06-25

申请号：US11960398

申请日：2007-12-19

Applicant: Richard Mellitz

Inventor： Richard Mellitz

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: Embodiments of the invention include a Printed Wiring Board (PWB) having a first via connected to a top-side signal source, a second via connected to a bottom-side signal destination, and a third via connected to the first via on a lower signal layer of the PWB and further connected to the second via on an upper signal layer of the PWB. In embodiments of the invention, the third via is referred to as an S-Turn via. The S-Turn PWB routing configuration advantageously reduces reflections causes by via stubs at Multi-Giga Hertz (MGH) frequencies. Other embodiments are described.

Abstract translation: 本发明的实施例包括具有连接到顶侧信号源的第一通孔的印刷布线板（PWB），连接到底侧信号目的地的第二通孔和连接到下侧信号的第一通孔的第三通孔 层，并且在PWB的上信号层上进一步连接到第二通孔。 在本发明的实施例中，第三通孔被称为S转弯通孔。 S-Turn PWB路由配置有利于减少通过多千兆赫兹（MGH）频率的存根造成的反射。 描述其他实施例。

公开(公告)号：US07550826B2

公开(公告)日：2009-06-23

申请号：US11702971

申请日：2007-02-06

Applicant: Kelly M. Orth ,  Chad M. McGuire

Inventor： Kelly M. Orth ,  Chad M. McGuire

IPC: H01L23/552

CPC classification number: H05K9/0049 ,  H01L2224/48091 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/112 ,  H05K7/1462 ,  H05K9/0052 ,  H05K2201/0723 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10151 ,  H01L2924/00014

Abstract: A field hardened industrial device is described with a housing of the device having electrically conductive walls surrounding a cavity with an open end. An electronics assembly is adapted to fit within the cavity. The device includes a circuit card assembly, which is a multi-layered printed wiring board with pass-through electrical connections and an embedded ground plane electrically coupled to the housing to shield the electronics assembly from electromagnetic interference and to provide environmental protection to the electronics assembly.

Abstract translation: 描述了一种场强淬火的工业装置，该装置的壳体具有围绕具有开口端的空腔的导电壁。 电子组件适于装配在腔内。 该装置包括电路卡组件，其是具有通过电连接的多层印刷布线板和电耦合到壳体的嵌入式接地平面，以屏蔽电子组件免受电磁干扰并向电子组件提供环境保护 。

公开(公告)号：US20090079523A1

公开(公告)日：2009-03-26

申请号：US12190597

申请日：2008-08-13

Applicant: Ti-Ming Hsu

Inventor： Ti-Ming Hsu

IPC: H01P3/08

CPC classification number: H01P3/026 ,  H01P3/081 ,  H01P5/028 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09627 ,  H05K2201/0969

Abstract: A layout of a circuit board includes a first signal layer, a second signal layer, and a third signal layer. The first signal layer has a transmission line. The second signal layer is stacked below the first signal layer, and has an opening. The third signal layer is stacked below the first and second signal layers with the second signal layer sandwiched between the first and third signal layers. The third signal layer is electrically connected to the second signal layer, and both of the second and third signal layers are ground layers or power layers. An orthogonal projection of a segment of the transmission line on the third signal layer is overlapped with that of the opening on the third signal layer. Therefore, an equivalent impedance of the segment of the transmission line referring to the second and third signal layers can be increased or decreased.

Abstract translation: 电路板的布局包括第一信号层，第二信号层和第三信号层。 第一信号层具有传输线。 第二信号层堆叠在第一信号层下方，并且具有开口。 第三信号层堆叠在第一和第二信号层之下，第二信号层夹在第一和第三信号层之间。 第三信号层电连接到第二信号层，第二信号层和第三信号层都是接地层或功率层。 第三信号层上的传输线段的正交投影与第三信号层上的开口的正交投影重叠。 因此，可以增加或减少参考第二和第三信号层的传输线段的等效阻抗。

公开(公告)号：US07508681B2

公开(公告)日：2009-03-24

申请号：US11808642

申请日：2007-06-12

Applicant: Jason J. Payne ,  Mark W. Gailus ,  Leon M. Khilchenko ,  Huilin Ren

Inventor： Jason J. Payne ,  Mark W. Gailus ,  Leon M. Khilchenko ,  Huilin Ren

IPC: H05K1/11

CPC classification number: H01R13/6477 ,  H01R12/714 ,  H01R13/514 ,  H01R13/6471 ,  H01R13/6587 ,  H05K1/0219 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/10189

Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias. For each of the plurality of rows of the conductive vias, there are at least twice as many ground conductor connecting conductive vias as signal conductor connecting conductive vias and the conductive vias are positioned relative to one another so that for each signal conductor connecting conductive via, there are ground conductor connecting conductive vias adjacent either side of the signal conductor connecting conductive via.

Abstract translation: 在优选实施例中，公开了一种印刷电路板，其具有提供配合接口的表面，电连接器具有信号导体和接地导体。 印刷电路板包括多个堆叠的电介质层，其中导体设置在多个电介质层中的至少一个上。 配合接口包括以多行排列的多个导电通孔，多个导电通孔延伸穿过多个电介质层的至少一部分，多个导电通孔中的至少一个与导体相交。 多个导电通孔包括连接导电通孔的信号导体和连接导电通孔的接地导体。 对于导电通孔的多行中的每一行，存在至少两倍的接地导体，其连接导电通孔，作为连接导电通孔的信号导体，并且导电通孔相对于彼此定位，使得对于连接导电通孔的每个信号导体， 有接地导体连接导电通孔，邻近信号导体的任一侧连接导电通孔。

公开(公告)号：US20090038840A1

公开(公告)日：2009-02-12

申请号：US12222057

申请日：2008-07-31

Applicant: Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

Inventor： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC: H05K9/00

CPC classification number: H05K9/0039 ,  H01P1/2005 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: Disclosed are an electromagnetic bandgap structure and a printed circuit board including the same. In accordance with an embodiment of the present invention, the printed circuit board can include a dielectric layer, a plurality of conductive plates, and a stitching via, which is configured to electrically connect the conductive plates to each other. The stitching via can pass through the dielectric layer, and a part of the stitching via can be placed in a planar surface that is different from a planar surface in which the conductive plates are placed. With the present invention, the electromagnetic bandgap structure can prevent a signal of a predetermined frequency band from being transferred.

Abstract translation: 公开了一种电磁带隙结构和包括该电阻带隙结构的印刷电路板。 根据本发明的实施例，印刷电路板可以包括介电层，多个导电板和缝合通孔，其被配置为将导电板彼此电连接。 缝合通孔可以穿过介电层，并且缝合通孔的一部分可以放置在与放置导电板的平坦表面不同的平面表面中。 利用本发明，电磁带隙结构可以防止预定频带的信号被传送。

公开(公告)号：US07476814B2

公开(公告)日：2009-01-13

申请号：US11603239

申请日：2006-11-22

Applicant: Yoshiteru Ochi ,  Nobutaka Itoh

Inventor： Yoshiteru Ochi ,  Nobutaka Itoh

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09827

Abstract: A multilayer interconnection board includes a plurality of stacked insulation layers, wiring layers in the insulation layers, and via forming parts for interlayer connection, the via forming parts piercing the insulation layers. In the multilayer interconnection board, 0

Abstract translation: 多层互连板包括多个堆叠绝缘层，绝缘层中的布线层和用于层间连接的通孔形成部件，穿孔绝缘层的通孔形成部件。 在多层互连板中，设定0

公开(公告)号：US20090008139A1

公开(公告)日：2009-01-08

申请号：US11772904

申请日：2007-07-03

Applicant: Patrik Lundell ,  Stefan Eskilsson ,  Thomas Ahlberg

Inventor： Patrik Lundell ,  Stefan Eskilsson ,  Thomas Ahlberg

IPC: H05K1/18 ,  H05K1/00 ,  H05K3/00

CPC classification number: H05K1/0253 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09627 ,  Y10T29/49155

Abstract: A multilayered printed wiring board, a multilayer PWB, and a method for manufacturing the same. The multilayer PWB comprises a first main surface and an opposing second main surface, where the multilayer PWB has a height being defined by the distance from the first main surface to the opposing second main surface. The two surfaces and the height together define the thickness of the multilayer PWB. The multilayer PWB comprises a reference ground plane, a microstrip conductor separated from the reference ground plane by a first dielectric layer and a stripline conductor connected with the microstrip conductor and being separated from the reference ground plane by a second dielectric layer. The reference ground plane is formed by two or more different partial reference ground planes positioned at different layers of the multilayer PWB. Furthermore, the reference ground plane is moveable from the first partial reference ground plane to the second partial reference ground plane when a signal current transits from the microstrip conductor to the stripline conductor, and vice versa.

Abstract translation: 多层印刷布线板，多层印刷电路板及其制造方法。 多层PWB包括第一主表面和相对的第二主表面，其中多层PWB具有由第一主表面到相对的第二主表面的距离限定的高度。 两个表面和高度一起限定了多层PWB的厚度。 多层PWB包括参考接地平面，通过第一电介质层与参考接地层分离的微带线导体和与微带导体连接的带状线导体，并通过第二电介质层与基准接地平面分离。 参考接地层由位于多层PWB的不同层的两个或多个不同的部分参考接地层形成。 此外，当信号电流从微带导体转移到带状线导体时，参考接地层可以从第一部分参考接地层移动到第二部分参考接地层，反之亦然。

公开(公告)号：US07459796B2

公开(公告)日：2008-12-02

申请号：US11410560

申请日：2006-04-24

Applicant: Masaaki Yanaka

Inventor： Masaaki Yanaka

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H05K1/114 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: Provided is a BGA-type multilayer circuit wiring board which is mounted on a printed wiring board directly via a solder ball with the electrode pad for solder ball connection formed thereon and in which the electric connection reliability of the filled via connected to the electrode pad for solder ball connection is not worsened. A wiring layer is formed on both surfaces of an insulating substrate; an electrode pad for solder bump for mounting a semiconductor chip thereon is formed on one surface of the substrate via an insulating layer; and an electrode pad for solder ball for connecting the structure to a printed wiring board is formed on the other surface thereof. The electrode pad for solder ball is electrically connected to the filled via; and the filled via is disposed in the intermediate position between the neighboring electrode pads for solder ball connection.

Abstract translation: 提供了一种BGA型多层电路布线板，其通过焊球直接安装在印刷布线板上，形成有用于焊球连接的电极焊盘，其中连接到电极焊盘的填充通孔的电连接可靠性 焊球连接不会恶化。 布线层形成在绝缘基板的两面上; 通过绝缘层在基板的一个表面上形成用于将半导体芯片安装在其上的用于焊料凸块的电极焊盘; 并且在其另一个表面上形成用于将结构连接到印刷线路板的用于焊球的电极焊盘。 用于焊球的电极焊盘与填充的通孔电连接; 并且填充的通孔设置在用于焊球连接的相邻电极焊盘之间的中间位置。

公开(公告)号：US07453704B2

公开(公告)日：2008-11-18

申请号：US11404771

申请日：2006-04-17

Applicant: Makoto Tanaka ,  Yuichi Koga

Inventor： Makoto Tanaka ,  Yuichi Koga

IPC: H05K7/00

CPC classification number: G06F1/1616 ,  G06F1/1656 ,  G06F1/18 ,  H01L2224/16225 ,  H01L2924/10158 ,  H01L2924/15311 ,  H05K1/114 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged on a surface of a first semiconductor chip, second pads provided on the reverse side in a second region defined thereon and overlapping with the first region, and to be connected to terminals arranged on a surface of a second semiconductor chip, and interlayer wiring electrically connecting those of the first pads, which are located in an overlapping region, to those of the second pads which are located in the overlapping region.

Abstract translation: 根据一个实施例，印刷电路板包括：主体，其具有正面和正面布线层的正面;反面具有反面布线层，第一焊盘设置在其上限定的第一区域的正面上，并且为 连接到布置在第一半导体芯片的表面上的端子，在限定在其上并与第一区域重叠的第二区域中的反面上设置的第二焊盘，并且连接到布置在第二半导体芯片的表面上的端子，以及 将位于重叠区域中的第一焊盘电连接到位于重叠区域中的第二焊盘的层间布线。

公开(公告)号：US20080271914A1

公开(公告)日：2008-11-06

申请号：US12168508

申请日：2008-07-07

Applicant: Makoto Tanaka ,  Yuichi Koga

Inventor： Makoto Tanaka ,  Yuichi Koga

IPC: H05K1/11

CPC classification number: G06F1/1616 ,  G06F1/1656 ,  G06F1/18 ,  H01L2224/16225 ,  H01L2924/10158 ,  H01L2924/15311 ,  H05K1/114 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged on a surface of a first semiconductor chip, second pads provided on the reverse side in a second region defined thereon and overlapping with the first region, and to be connected to terminals arranged on a surface of a second semiconductor chip, and interlayer wiring electrically connecting those of the first pads, which are located in an overlapping region, to those of the second pads which are located in the overlapping region.

Abstract translation: 根据一个实施例，印刷电路板包括：主体，其具有正面和正面布线层的正面;反面具有反面布线层，第一焊盘设置在其上限定的第一区域的正面上，并且为 连接到布置在第一半导体芯片的表面上的端子，在限定在其上并与第一区域重叠的第二区域中的反面上设置的第二焊盘，并且连接到布置在第二半导体芯片的表面上的端子，以及 将位于重叠区域中的第一焊盘电连接到位于重叠区域中的第二焊盘的层间布线。