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    MULTI-LAYER SUBSTRATE
    41.
    发明申请
    MULTI-LAYER SUBSTRATE 有权
    多层基板

    公开(公告)号：US20100282503A1

    公开(公告)日：2010-11-11

    申请号：US12675678

    申请日：2007-08-31

    Applicant: Taras Kushta

    Inventor： Taras Kushta

    IPC: H05K1/11

    CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781

    Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.

    Abstract translation: 多层基板包括通过多层转换连接的平面传输线结构和信号通孔。 多层转换包括经配置以用于信号通孔和平面传输线的全值连接的信号通孔; 以及连接到信号通孔的虚拟焊盘，形成在设置在信号通孔的信号端子和平面传输线之间并与导体层隔离的导体层中的间隙孔的区域中。

    KU-BAND DIPLEXER
    43.
    发明申请
    KU-BAND DIPLEXER 有权

    公开(公告)号：US20100188167A1

    公开(公告)日：2010-07-29

    申请号：US12376738

    申请日：2007-09-07

    Applicant: Jeff Devereux ,  Fritz Gerd Berger ,  William A. Johnston ,  Mohammad Ali Tassoudji ,  Scott Aldern

    Inventor： Jeff Devereux ,  Fritz Gerd Berger ,  William A. Johnston ,  Mohammad Ali Tassoudji ,  Scott Aldern

    IPC: H01P5/12

    CPC classification number: H01P5/085 ,  H05K1/0243 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09718 ,  H05K2201/09809 ,  Y10T29/49139

    Abstract: A compact Ku band microwave diplexer configured as a three port surface mount component on a miniature alumina substrate. Input signals occurring at a common port having frequencies within a first pass band are passed to a second port while being isolated from signals occurring at a third port. Signals occurring at the third port are passed to the common port while being isolated from the signals at the second port. A microstrip dual spur line filter is used combined with open circuit stubs to provide enhanced second harmonic suppression on the transmit side, while using a coupled line microstrip filter on the receive side. This approach allows for compact size and automated component assembly through pick and place and reflow manufacturing techniques.

    Abstract translation: 在微型氧化铝基板上构造为三端口表面安装部件的紧凑型Ku波段微波双工器。 在具有第一通带内的频率的公共端口处发生的输入信号被传递到第二端口，同时与在第三端口处发生的信号隔离。 在第三个端口发生的信号被传递到公共端口，同时与第二个端口的信号隔​​离。 微带双支路线路滤波器与开路短路组合使用，以在发射侧提供增强的二次谐波抑制，同时在接收侧使用耦合线路微带滤波器。 这种方法允许通过拾取和放置和回流制​​造技术实现紧凑的尺寸和自动部件组装。

    Printed circuit board having vias
    44.
    发明授权
    Printed circuit board having vias 有权
    具有通孔的印刷电路板

    公开(公告)号：US07745737B2

    公开(公告)日：2010-06-29

    申请号：US11478922

    申请日：2006-06-30

    Applicant: Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

    Inventor： Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

    IPC: H01R12/04 ,  H05K1/11 ,  H01K3/22

    CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718 ,  Y10T29/49165

    Abstract: A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

    Abstract translation: 具有用于减少输入信号的反射的通孔的印刷电路板（PCB）包括第一信号层，第二信号层，一个通孔，布置在第一信号层上的输入信号线和布置在第二信号上的输出信号线 层。 通孔还包括钻孔，第一垫和第二垫。 第一焊盘与输入信号线电连接，第二焊盘与输出信号线电连接。 第一垫的外径小于第二垫的外径。

    Microelectronic device including bridging interconnect to top conductive layer of passive embedded structure and method of making same
    45.
    发明授权
    Microelectronic device including bridging interconnect to top conductive layer of passive embedded structure and method of making same 有权
    微电子器件包括桥接互连到被动嵌入式结构的顶层导电层及其制造方法

    公开(公告)号：US07738257B2

    公开(公告)日：2010-06-15

    申请号：US11610385

    申请日：2006-12-13

    Applicant: Islam Salama ,  Yongki Min ,  Huankiat Seh

    Inventor： Islam Salama ,  Yongki Min ,  Huankiat Seh

    IPC: H05K1/18

    CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09718 ,  H05K2201/09918 ,  H05K2203/0353 ,  Y10T29/4913 ,  Y10T29/49155

    Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.

    Abstract translation: 微电子器件，制造该器件的方法以及包括该器件的系统。 该装置包括：包含聚合物累积层的基底和嵌入基底中的被动结构。 被动结构包括覆盖聚合物积聚层的顶部导电层，覆盖顶部导电层的电介质层和覆盖在电介质层上的底部导电层。 该器件还包括延伸穿过聚合物积聚层并与底部导电层电绝缘的导电通孔，将导电通孔与底部导电层绝缘的绝缘材料以及布置在顶部导电层侧面的桥接互连 背离电介质层，桥接互连将导电通孔电连接到顶部导电层。

    Semiconductor package substrate
    46.
    发明授权
    Semiconductor package substrate 有权
    半导体封装基板

    公开(公告)号：US07732913B2

    公开(公告)日：2010-06-08

    申请号：US11701767

    申请日：2007-02-02

    Applicant: Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    Inventor： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    IPC: H01L23/04

    CPC classification number: H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

    Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

    Abstract translation: 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

    PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME
    49.
    发明申请
    PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME 有权
    印刷线路板及其制造方法

    公开(公告)号：US20100065321A1

    公开(公告)日：2010-03-18

    申请号：US12557371

    申请日：2009-09-10

    Applicant: KAZUHIRO KASHIWAKURA

    Inventor： KAZUHIRO KASHIWAKURA

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/09718 ,  Y10T29/49124 ,  Y10T29/49155

    Abstract: A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes formed at predetermined positions along a circle concentric with a center axis of the first through hole; clearances provided between the first through hole and each of the ground layers; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance docs not contact with the second through holes. The second through holes arc not connected to the ground layers that are not adjacent to the signal wiring but are connected to the ground layer neighboring layer in which the signal wiring is disposed.

    Abstract translation: 印刷电路板包括通过绝缘体堆叠的接地层; 第一个通孔; 沿着与所述第一通孔的中心轴同心的圆的预定位置形成的第二通孔; 间隙设置在第一通孔和每个接地层之间; 以及信号布线，其各自从第一通孔延伸穿过位于第二通孔的预定第二通孔之间的预定接地层之间的间隙。 其中布置信号布线的地层相邻层中的每个第一间隙具有第一通孔之间的距离和第一间隙的轮廓线是信号布线最小的轮廓。 与信号线不相邻的接地层中的每个第二间隙具有形成在围绕第一信号通孔的第二通孔的每个中心的圆周外的轮廓，使得第二间隙的轮廓不与第二通孔接触。 第二通孔不连接到不与信号线相邻的接地层，而是连接到布置信号布线的接地层相邻层。

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