公开(公告)号：US08272126B2

公开(公告)日：2012-09-25

申请号：US12431950

申请日：2009-04-29

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H05K3/02

CPC classification number: H05K3/184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/023 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/11 ,  H05K1/162 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/09381 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0108 ,  H05K2203/0565 ,  H05K2203/161 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An object of an aspect of the present invention is to provide a method of producing a circuit board that allows highly accurate preservation of the circuit profile and gives a circuit having a desired depth in preparation of a fine circuit by additive process.The method of producing a multilayer circuit board in an aspect of the present invention includes a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the swellable resin film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the swellable resin film.

Abstract translation: 本发明的一个方面的目的是提供一种电路板的制造方法，其能够高精度地保存电路剖面，并且通过加法处理给出具有所需深度的电路以准备精细电路。 在本发明的一个方面中，制造多层电路板的方法包括：在绝缘性基板的表面上形成可溶胀树脂膜的成膜工序;形成电路槽的电路槽形成工序，其深度等于 或大于可溶胀树脂膜的外表面上的可溶胀树脂膜的厚度，在电路槽的表面和可溶胀树脂膜的表面上沉积电镀催化剂或其前体的催化剂沉积步骤， 使用特定液体使溶胀性树脂膜溶胀，然后将所述溶胀树脂膜与所述绝缘性基板表面分离的膜分离工序，以及仅在所述镀催化剂或所述镀层的区域形成无电镀膜的电镀处理工序 在可溶胀树脂膜分离之后，由电镀催化剂前体形成的催化剂保持未分离。

公开(公告)号：US20120206891A1

公开(公告)日：2012-08-16

申请号：US13504281

申请日：2010-10-28

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H05K7/06 ,  H05K1/02

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board H10 according to the present invention is a circuit board H10 in which an electric circuit H6 including a wiring section H6a and a pad section H6b is provided in the surface of an insulating base substrate H1. The electric circuit H6 is configured such that a conductor H5 is embedded in a circuit recess H3 formed in the surface of the insulating base substrate H1, and the surface roughness of the conductor H5 is different in the wiring section H6a and the pad section H6b of the electric circuit H6. In this case, it is preferable that the surface roughness of the conductor H5 in the pad section H6b is greater than the surface roughness of the conductor H5 in the wiring section H6a.

Abstract translation: 根据本发明的电路板H10是电路板H10，其中包括布线部分H6a和焊盘部分H6b的电路H6设置在绝缘基板H1的表面中。 电路H6被配置为使得导体H5嵌入在形成在绝缘性基板H1的表面上的电路凹部H3中，并且导体H5的表面粗糙度在布线部H6a和焊盘部H6b中不同 电路H6。 在这种情况下，优选的是，焊盘部H6b中的导体H5的表面粗糙度大于布线部H6a中的导体H5的表面粗糙度。

公开(公告)号：US08232642B2

公开(公告)日：2012-07-31

申请号：US12835043

申请日：2010-07-13

Applicant: Seong Cheol Kim ,  Chang Jun Park

Inventor： Seong Cheol Kim ,  Chang Jun Park

IPC: H01L23/488

CPC classification number: H01L23/488 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3511 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/0191 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09736 ,  Y02P70/613

Abstract: A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a height that increases from edges toward a center of the warpage compensating part so that an upper surface of the warpage compensating part facing away from the first surface of the body part is convex upward. The warpage compensating part comprises conductive layer patterns formed over the first surface of the body part to be electrically connected to the connection pads; and a solder resist formed over the first surface of the body part so as to expose the conductive layer patterns. The height of the solder resist gradually increases from both edges toward a center of the solder resist.

Abstract translation: 印刷电路板包括在其第一表面上形成有连接焊盘的主体部分; 以及翘曲补偿部，其形成在主体部的第一表面上，并且具有从边缘朝向翘曲补偿部的中心增加的高度，使得翘曲补偿部的上表面背离主体部的第一表面 向上凸起 翘曲补偿部分包括形成在主体部分的第一表面上以电连接到连接焊盘的导电层图案; 以及形成在主体部分的第一表面上的阻焊剂，以暴露导电层图案。 阻焊剂的高度从阻焊层的两个边缘向中心逐渐增加。

公开(公告)号：US08221635B2

公开(公告)日：2012-07-17

申请号：US12712430

申请日：2010-02-25

Applicant: John W. Hauff

Inventor： John W. Hauff

IPC: H01B13/00 ,  B44C1/22

CPC classification number: H05K3/06 ,  H05K1/0237 ,  H05K1/0265 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/09972 ,  H05K2203/1476

Abstract: A process for manufacturing a printed wiring board includes specifying overlapping etches for a first portion of the printed wiring board and a second portion of the printed wiring board, the first portion of the printed wiring board having disposed thereon a printed circuit having at least one dimension critical to printed wiring board operation, etching a first conductor in the first portion of the printed wiring board when a first conductor thickness is a predetermined thickness, completing all plating steps, and etching a second conductor in the second portion of the printed wiring board.

Abstract translation: 一种制造印刷电路板的方法，包括：对印刷电路板的第一部分和印刷线路板的第二部分进行重叠蚀刻，印刷线路板的第一部分设置有印刷电路，印刷电路具有至少一个尺寸 对印刷线路板操作至关重要，当第一导体厚度为预定厚度时，蚀刻印刷电路板的第一部分中的第一导体，完成所有电镀步骤，以及蚀刻印刷线路板的第二部分中的第二导体。

公开(公告)号：US08198538B2

公开(公告)日：2012-06-12

申请号：US12392272

申请日：2009-02-25

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang ,  Ray-Fong Hong

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang ,  Ray-Fong Hong

IPC: H05K1/09

CPC classification number: H05K1/162 ,  H01G4/228 ,  H01G4/248 ,  H01G4/33 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/112 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10674

Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.

Abstract translation: 提供了一种电容器件。 该电容性装置包括第一电极和第一电极之下并与第一电极间隔开的第二电极，其中第一电极和第二电极中的至少一个包括多个导电步骤部分，所述多个导电步骤部分具有 不同的高度 电容性装置还包括在第一电极和第二电极之间的绝缘区域; 以及形成在第一电极和第二电极之一上的至少一个槽。

公开(公告)号：US20120103931A1

公开(公告)日：2012-05-03

申请号：US13347022

申请日：2012-01-10

Applicant: Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Akihiro Miyata ,  Fumitaka Takagi

Inventor： Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Akihiro Miyata ,  Fumitaka Takagi

IPC: H05K3/06

CPC classification number: C23F1/02 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K3/108 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/049 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract translation: 一种制造印刷电路板的方法，包括在绝缘板的表面上形成金属膜，在金属膜上形成电镀抗蚀剂，以及在电镀抗蚀剂暴露的金属膜上的镀金属膜，覆盖一部分 具有抗蚀剂的电镀金属膜，蚀刻以减少从抗蚀剂暴露的电镀金属膜的厚度，去除蚀刻和电镀抗蚀剂，以及形成具有用于将电子部件的电极引线接合的焊盘的布线，以及 通过去除在电镀抗蚀剂之后暴露的金属膜而比焊盘更薄的导电电路被去除，在该板和布线的表面上的阻焊层，暴露该焊盘的该层中的一个开口和该电路的一部分与 焊盘和焊盘上的金属涂层以及通过开口露出的电路部分。

公开(公告)号：US08153905B2

公开(公告)日：2012-04-10

申请号：US12685716

申请日：2010-01-12

Applicant: Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

Inventor： Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/108 ,  H05K3/3484 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/043 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/0401

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the resists, and forming a wiring having a pad and a conductive circuit thinner than the pad by removing the metal film exposed through the removing of the plating resist, a solder-resist layer on the surface of the board and wiring, in the layer an opening exposing the pad and a portion of the circuit contiguous to the pad, a solder film on the pad and portion of the circuit exposed through the opening, and a solder bump on the pad by solder reflow.

Abstract translation: 一种制造印刷电路板的方法，包括在绝缘板的表面上形成金属膜，在金属膜上形成电镀抗蚀剂，以及在电镀抗蚀剂暴露的金属膜上的镀金属膜，覆盖一部分 具有抗蚀剂的镀金属膜，蚀刻以减少从抗蚀剂暴露的镀金属膜的厚度，去除抗蚀剂，以及通过除去暴露的金属膜，形成具有焊盘和比焊盘更薄的导电电路的布线 通过去除电镀抗蚀剂，在基板和布线的表面上形成阻焊层，在该层中，露出焊盘的开口和与焊盘相邻的电路的一部分，焊盘上的焊料膜和 通过开口暴露的电路，以及通过焊料回流焊盘上的焊料凸块。

公开(公告)号：US20120011716A1

公开(公告)日：2012-01-19

申请号：US13137695

申请日：2011-09-02

Applicant: Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

Inventor： Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

IPC: H05K3/42

CPC classification number: H05K3/462 ,  H05K1/0265 ,  H05K1/0366 ,  H05K3/025 ,  H05K3/108 ,  H05K3/4623 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board including: preparing a first double-sided substrate including a first insulating layer, a first lower copper layer, a second circuit layer including a first lower land, and a first via; preparing a second double-sided substrate including a second insulating layer, a third lower copper layer, a fourth circuit layer including a second lower land, and a second via; disposing a third insulating layer between the second circuit layer and the fourth circuit layer such that the first lower land and the second lower land are electrically connected to each other though a conductive bump; and forming a first circuit layer including a first circuit pattern connected to the first via on the first lower copper layer and forming a third circuit layer including a third circuit pattern connected to the second via on the third lower copper layer.

Abstract translation: 一种制造印刷电路板的方法，包括：制备包括第一绝缘层，第一下铜层，包括第一下焊盘的第二电路层和第一通孔的第一双面基板; 制备包括第二绝缘层，第三下铜层，包括第二下焊盘的第四电路层和第二通孔的第二双面基板; 在所述第二电路层和所述第四电路层之间设置第三绝缘层，使得所述第一下焊盘和所述第二下焊盘通过导电凸块彼此电连接; 以及形成第一电路层，所述第一电路层包括在所述第一下铜层上连接到所述第一通孔的第一电路图案，并形成第三电路层，所述第三电路层包括在所述第三下铜层上连接到所述第二通孔的第三电路图案。

公开(公告)号：US20120006591A1

公开(公告)日：2012-01-12

申请号：US13176876

申请日：2011-07-06

Applicant: Kentaro Kaneko ,  Kotaro Kodani ,  Kazuhiro Kobayashi ,  Junichi Nakamura

Inventor： Kentaro Kaneko ,  Kotaro Kodani ,  Kazuhiro Kobayashi ,  Junichi Nakamura

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/205 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15174 ,  H05K1/113 ,  H05K3/244 ,  H05K2201/09736 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

Abstract: A wiring substrate that prevents the occurrence of delamination near an interface between an insulation layer and an electrode pad, which is formed in a recess of the insulation layer. An adjustment layer is formed in an opening in a resist, which is applied to a support body, to adjust the shape of the electrode pad. The adjustment layer includes a flat surface, which is substantially parallel to the support body, and an inclined surface, which extends from a rim of the flat surface toward the support body and to the side wall of the opening. A pad body of the electrode pad and an insulation layer including a wire is formed on the adjustment layer. The support body and adjustment layer are etched to expose the pad body.

Abstract translation: 一种布线基板，其防止在绝缘层的凹部中形成的绝缘层和电极焊盘之间的界面附近发生分层。 在抗蚀剂的开口中形成调整层，其被施加到支撑体上，以调节电极垫的形状。 调整层包括基本上平行于支撑体的平坦表面和从平坦表面的边缘朝向支撑体延伸到开口的侧壁的倾斜表面。 在调整层上形成有电极焊盘的焊盘主体和包括导线的绝缘层。 蚀刻支撑体和调整层以露出垫体。

公开(公告)号：US08084696B2

公开(公告)日：2011-12-27

申请号：US12428776

申请日：2009-04-23

Applicant: Tae-Gui Kim ,  Young-Hwan Shin ,  Jae-Soo Lee ,  Tae-Gon Lee

Inventor： Tae-Gui Kim ,  Young-Hwan Shin ,  Jae-Soo Lee ,  Tae-Gon Lee

IPC: H05K1/11

CPC classification number: H05K3/0035 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/108 ,  H05K3/243 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09736 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board and a method of manufacturing the same are disclosed. The method of manufacturing a printed circuit board including a connecting layer configured to which is configured to electrically connect both sides of an insulator, and a pad part, electrically connect both sides of an insulator, and a pad part formed in one side of the insulator to be directly in contact with the connecting layer, includes: forming a seed layer part on one side of the insulator, a portion of the seed layer part being bulged, forming a via hole by processing the other side of the insulator, corresponding to the bulged portion of the seed layer part, forming the connecting layer inside the via hole, and forming a plating layer, corresponding to the pad part, on the seed layer part. A pattern having a finer pitch, maintaining a VOP structure, can be formed and a lower side of a substrate is not penetrated through when a via hole is processed.

Abstract translation: 公开了一种印刷电路板及其制造方法。 制造印刷电路板的方法包括：被配置为电连接绝缘体的两侧的连接层和电连接绝缘体的两侧的焊盘部分和形成在绝缘体的一侧的焊盘部分的连接层 与连接层直接接触的方法包括：在绝缘体的一侧形成种子层部分，种子层部分的一部分被凸起，通过加工绝缘体的另一侧形成通孔，对应于 种子层部分的隆起部分，在通孔内形成连接层，并在种子层部分上形成对应于焊盘部分的镀层。 当形成通孔时，可以形成具有更细的间距，保持VOP结构的图案，并且当基板的下侧不被穿透时。