公开(公告)号：US20070164445A1

公开(公告)日：2007-07-19

申请号：US11650459

申请日：2007-01-08

Applicant: Daisuke Ejima

Inventor： Daisuke Ejima

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/13 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09772 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Aiming at adjusting the height of bump electrodes connected to lands on a substrate, a semiconductor device 100 has a first interconnect substrate 103 and a second interconnect substrate 101. On one surface of these substrates, first lands 111 and second lands 113 are provided. The plane geometry of the second lands 113 is a polygon characterized by the inscribed circle thereof having an area smaller than the area of the inscribed circle of the first land.

Abstract translation: 为了调整连接到衬底上的焊盘的凸起电极的高度，半导体器件100具有第一互连衬底103和第二互连衬底101。 在这些基板的一个表面上，设置有第一焊盘111和第二焊盘113。 第二平台113的平面几何形状是其内接圆的面积小于第一平台的内切圆的面积的多边形。

公开(公告)号：US20070109709A1

公开(公告)日：2007-05-17

申请号：US10582758

申请日：2004-12-22

Applicant: David Anthony ,  Anthony Anthony ,  William Anthony ,  James Muccioli ,  Richard Neifeld

Inventor： David Anthony ,  Anthony Anthony ,  William Anthony ,  James Muccioli ,  Richard Neifeld

IPC: H02H9/06

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An energy conditioner structure comprising a first electrode (120), a second electrode (80), and a shield structure (70, 110, 150) provides improved energy conditioning in electrical circuits. The structures may exist as discrete components or part of an integrated circuit. The shield structure in the energy conditioner structure does not electrically connect to any circuit element.

Abstract translation: 包括第一电极（120），第二电极（80）和屏蔽结构（70,110,150）的能量调节器结构在电路中提供改进的能量调节。 结构可以作为分立组件或集成电路的一部分存在。 能量调节器结构中的屏蔽结构不电连接到任何电路元件。

公开(公告)号：US20070051535A1

公开(公告)日：2007-03-08

申请号：US11308935

申请日：2006-05-29

Applicant: CHIH-CHAN GER ,  YU-HSIANG LIAO

Inventor： CHIH-CHAN GER ,  YU-HSIANG LIAO

IPC: H05K1/16

CPC classification number: H05K1/141 ,  H01L2224/48091 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/181 ,  H05K3/328 ,  H05K3/3426 ,  H05K3/3442 ,  H05K2201/09772 ,  H05K2201/1003 ,  H05K2201/10189 ,  H05K2201/10469 ,  H05K2201/10651 ,  H05K2201/10659 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device includes an electronic component (40), a first printed circuit board (PCB) (100) and a second printed circuit board (200). The electronic component includes a first pin (A1) and a second pin (A2). The first PCB and a second PCB, respectively including first conductor trace lines (102) and second conductor trace lines (108) for electrically connecting the first pin and the second pin. The first PCB is disposed above the second PCB, and is parallel with the second PCB. The first PCB is electrically connected to the second PCB via at least one of the first conductor trace lines and the second conductor trace lines. A surface area of the first PCB is smaller than that of the second PCB.

Abstract translation: 电子设备包括电子部件（40），第一印刷电路板（PCB）（100）和第二印刷电路板（200）。 电子部件包括第一销（A 1）和第二销（A 2）。 第一PCB和第二PCB分别包括用于电连接第一引脚和第二引脚的第一导体迹线（102）和第二导体迹线（108）。 第一PCB设置在第二PCB上方，并与第二PCB平行。 第一PCB经由第一导体迹线和第二导体迹线中的至少一个电连接到第二PCB。 第一PCB的表面积小于第二PCB的表面积。

公开(公告)号：US20070013045A1

公开(公告)日：2007-01-18

申请号：US11257593

申请日：2005-10-24

Applicant: Chih-Hsiung Lin ,  Nai-Shung Chang

Inventor： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC: H01L23/48 ,  H01L23/28

CPC classification number: H05K1/0209 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10734

Abstract: A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

公开(公告)号：US20060263939A1

公开(公告)日：2006-11-23

申请号：US11460859

申请日：2006-07-28

Applicant: Kevin Lyne

Inventor： Kevin Lyne

IPC: H01L21/00

CPC classification number: H01L23/49816 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

公开(公告)号：US20050263846A1

公开(公告)日：2005-12-01

申请号：US11139238

申请日：2005-05-26

Applicant: Yasunori Inoue ,  Ryosuke Usui ,  Yasuhiro Kohara ,  Nobuhisa Takakusakai ,  Takeshi Nakamura

Inventor： Yasunori Inoue ,  Ryosuke Usui ,  Yasuhiro Kohara ,  Nobuhisa Takakusakai ,  Takeshi Nakamura

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L29/00 ,  H05K1/02 ,  H05K1/05 ,  H05K3/00 ,  H05K3/28 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L23/3735 ,  H01L21/4857 ,  H01L21/4871 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: In a manufacturing method of a hybrid integrated circuit device 10 according to the present invention, a first dummy pattern D1 is provided on a first wiring layer 18A. Furthermore, a second dummy pattern D2 is provided on a second wiring layer 18B. The first dummy pattern D1 and the second dummy pattern D2 are connected through a connection part 25 which penetrates an insulation layer 17. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.

Abstract translation: 在根据本发明的混合集成电路装置10的制造方法中，在第一布线层18A上设置第一虚设图案D 1。此外，第二布线层18B设置第二虚设图案D 2 第一虚设图案D 1和第二虚设图案D 2通过贯穿绝缘层17的连接部25连接。 因此，可以主动地执行通过虚拟图案的散热。 此外，即使在形成多层布线的情况下，也可以提供能够确保散热性的电路装置。

公开(公告)号：US06922338B2

公开(公告)日：2005-07-26

申请号：US10682649

申请日：2003-10-09

Applicant: Peter Poechmueller

Inventor： Peter Poechmueller

IPC: G11C5/00 ,  G11C7/04 ,  H05K7/20

CPC classification number: G11C5/005 ,  G11C5/143 ,  G11C7/04 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0209 ,  H05K3/28 ,  H05K2201/09263 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10159 ,  H05K2201/2018 ,  H01L2924/00

Abstract: A memory module includes a board, a memory device attached to the board, and a heat dissipation means arranged between the memory device and the board.

Abstract translation: 存储器模块包括板，连接到板的存储器件，以及布置在存储器件和板之间的散热器件。

公开(公告)号：US20040201971A1

公开(公告)日：2004-10-14

申请号：US10408951

申请日：2003-04-08

Inventor： John Thomas Fessler ,  Keith Bryan Hardin ,  Eric Wayne Westerfield

IPC: H05K001/11 ,  H05K007/06

CPC classification number: H05K1/0218 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09772 ,  H05K2201/10689

Abstract: A multi-layer printed circuit board (PCB) routes signal traces on internal signal layer(s) and includes power planes on the two outermost layers. The outer layers are maintained at the same non-ground voltage level, and are electrically connected by a series of vias that circumscribe signal traces on the internal layer(s). With a preferred maximum spacing of one-tenth the wavelength of electromagnetic energy generated by the signal traces, the vias, together with the outer power planes, contain electromagnetic energy within the PCB. One or more of the outer planes may include a second power plane area maintained at a different voltage. The two power plane areas are connected by decoupling capacitors, located proximate underlying signal traces that traverse the two power plane areas.

Abstract translation: 多层印刷电路板（PCB）在内部信号层上传送信号迹线，并且包括两个最外层的电源层。 外层保持在相同的非接地电压电平，并且通过一系列通孔来电连接，这些通孔围绕内层上的信号迹线。 通过由信号迹线产生的电磁能量波长的十分之一的优选最大间距，通孔与外部电源平面在PCB内包含电磁能。 一个或多个外平面可以包括维持在不同电压的第二电源平面区域。 两个电力平面区域通过去耦电容器连接，位于邻近穿过两个电源平面区域的底层信号迹线。

公开(公告)号：US20020158341A1

公开(公告)日：2002-10-31

申请号：US10123211

申请日：2002-04-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kei Murayama

IPC: H01L023/48

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/10318 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract translation: 一种半导体封装，其具有包括形成在绝缘基板或绝缘层上的互连图案和焊盘的互连层，覆盖所述焊盘部分以外的所述互连层的保护层和绝缘基板或绝缘层，以及外部连接端子 与从保护层暴露的焊盘接合，外部连接端子被接合到的焊盘由多个焊盘段组成，足够的空间被打开以通过焊盘段之间的互连，并且焊盘段至少包括 连接到互连的一个焊盘段和未连接到互连的其它焊盘段。

公开(公告)号：US06184494B2

公开(公告)日：2001-02-06

申请号：US09478584

申请日：2000-01-06

Applicant: Arto Isokoski ,  Jari Marjakangas

Inventor： Arto Isokoski ,  Jari Marjakangas

IPC: H05B100

CPC classification number: H05K1/0212 ,  H01L23/345 ,  H01L2924/0002 ,  H05K3/3494 ,  H05K3/429 ,  H05K2201/062 ,  H05K2201/09645 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H01L2924/00

Abstract: The present invention relates to a heating method and a printed circuit board comprising a heating element which generates heat required to heat printed circuit board components. The printed circuit board comprises heat conductor between the heating element and the component to be heated, the heat conductor receiving heat generated by the heating element and conducting the heat along the surface of the printed circuit board beneath the lower surface of the component to be heated. Furthermore, the printed circuit board comprises conductor parts which are narrower that the heat conductor, or which have a smaller cross-sectional surface area than does the heat conductor, and which restrict heat transfer away from the heat conductor to a component other than the one to be heated when the heat conductor functions as a ground plane or a signal path.

Abstract translation: 本发明涉及加热方法和印刷电路板，其包括产生加热印刷电路板部件所需的热的加热元件。 印刷电路板包括加热元件和待加热元件之间的导热体，热导体接收由加热元件产生的热量，并沿着待加热元件的下表面的印刷电路板表面传导热量 。 此外，印刷电路板包括导体部分，导体部分比热导体更窄，或者具有比导热体更小的横截面表面积，并且限制热传导远离热导体到除了导体之外的部件 当热导体用作接地平面或信号路径时被加热。