公开(公告)号：US07417872B2

公开(公告)日：2008-08-26

申请号：US11459951

申请日：2006-07-26

Applicant: Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

Inventor： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

IPC: H05H1/11

CPC classification number: H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract translation: 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有布置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US20080173477A1

公开(公告)日：2008-07-24

申请号：US11901371

申请日：2007-09-17

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H01L23/48

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract translation: 电路板包括薄膜基板，在薄膜基板上依次布置的多个布线层和分别形成在布线层上的凸起。 每个凸块跨越相应的一个布线层的纵向方向设置，以便在绝缘基板上方的布线层的两侧的区域上延伸，并且沿宽度方向的凸起的横截面形状 布线层的中心部分高​​于中央部分两侧的部分。 因此，形成在布线层上的突起可以抵抗在横向施加的力而实际使用的强度。

公开(公告)号：US20070122553A1

公开(公告)日：2007-05-31

申请号：US11699549

申请日：2007-01-30

Applicant: Akifumi Kamijima

Inventor： Akifumi Kamijima

IPC: B05D5/00

CPC classification number: C25D5/022 ,  H01F17/0006 ,  H01F41/042 ,  H01L27/08 ,  H05K1/165 ,  H05K3/108 ,  H05K2201/098 ,  H05K2203/0577 ,  H05K2203/1184 ,  Y10T428/12333 ,  Y10T428/12438 ,  Y10T428/12528 ,  Y10T428/12646 ,  Y10T428/12903

Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.

Abstract translation: 形成图案化薄膜的方法包括在电极膜上形成其底部附近具有底切的框架的步骤，以及通过使用框架通过电镀形成图案化薄膜的电镀步骤。 图案化薄膜包括并排设置的多个直线部分。 每个直线部分具有靠近电极膜的部分。 该部分的宽度大于每个直线部分的剩余部分的宽度。

公开(公告)号：US20070101571A1

公开(公告)日：2007-05-10

申请号：US10580948

申请日：2004-12-02

Applicant: Tatsuo Kataoka ,  Yoshikazu Akashi ,  Yutaka Iguchi

Inventor： Tatsuo Kataoka ,  Yoshikazu Akashi ,  Yutaka Iguchi

IPC: H05K3/00

CPC classification number: H05K3/06 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2201/098 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/5164

Abstract: [Solution means] A process for producing a printed wiring board comprises the steps of depositing a base metal on at least one surface of an insulating film to form a base metal layer and further depositing copper or a copper alloy to form a conductive metal layer, then removing a surface metal layer, which is formed through the above step, by etching to form a wiring pattern, and then treating the base metal layer with a treating liquid capable of dissolving and/or passivating the metal that forms the base metal layer. The printed wiring board so provided comprises an insulating film and a wiring pattern formed on at least one surface of the insulating film, the wiring pattern including a base metal layer deposited on the insulating film surface and a conductive metal layer, the base metal layer for forming the wiring pattern protrudes in a widthwise direction more than the conductive metal layer for forming the wiring pattern.

Abstract translation: [解决方案]印刷电路板的制造方法包括以下步骤：在绝缘膜的至少一个表面上沉积贱金属以形成贱金属层，并进一步沉积铜或铜合金以形成导电金属层， 然后通过蚀刻去除通过上述步骤形成的表面金属层以形成布线图案，然后用能够溶解和/或钝化形成基底金属层的金属的处理液处理基底金属层。 所提供的印刷电路板包括绝缘膜和形成在绝缘膜的至少一个表面上的布线图案，布线图案包括沉积在绝缘膜表面上的基底金属层和导电金属层，所述基底金属层用于 形成布线图案比形成布线图案的导电金属层的宽度方向突出。

公开(公告)号：US20050218496A1

公开(公告)日：2005-10-06

申请号：US11146802

申请日：2005-06-07

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H05K3/34 ,  H01L21/48 ,  H01L21/60 ,  H01L23/495 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract translation: 电路板包括薄膜基板，在薄膜基板上依次布置的多个布线层和分别形成在布线层上的凸起。 每个凸块跨越相应的一个布线层的纵向方向设置，以便在绝缘基板上方的布线层的两侧的区域上延伸，并且沿宽度方向的凸起的横截面形状 布线层的中心部分高​​于中央部分两侧的部分。 因此，形成在布线层上的突起可以抵抗在横向施加的力而实际使用的强度。

公开(公告)号：US06949470B2

公开(公告)日：2005-09-27

申请号：US10664333

申请日：2003-09-17

Applicant: Yusuke Igarashi ,  Hideki Mizuhara ,  Noriaki Sakamoto

Inventor： Yusuke Igarashi ,  Hideki Mizuhara ,  Noriaki Sakamoto

IPC: H01L23/12 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H05K1/18 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/28 ,  H01L21/302

CPC classification number: H05K3/205 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/538 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/07802 ,  H01L2924/15311 ,  H05K1/185 ,  H05K1/187 ,  H05K3/062 ,  H05K3/108 ,  H05K3/284 ,  H05K2201/098 ,  Y10T29/49146 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/49171 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.

Abstract translation: 优选地，其中使用具有导电图案的柔性片的半导体器件作为支撑衬底，在其上安装半导体元件，并且已经开发了组合。 在这种情况下，存在无法形成多层布线结构并且在制造工艺中绝缘树脂片翘曲突出的问题。 为了解决这些问题，通过层叠第一导电膜11和第二导电膜12而形成的层叠板10被具有带有倾斜面13S的开口部13的光致抗蚀剂层PR覆盖，导电布线层14形成在 通过电解电镀形成开口部，以形成倒置的倾斜面14R，然后当用密封树脂层21覆盖时，通过使密封树脂层21咬入倒置的倾斜表面14R而产生锚定效果，以便 以加强密封树脂层21与导电布线层14的接合。

公开(公告)号：US06798320B2

公开(公告)日：2004-09-28

申请号：US10059623

申请日：2002-01-29

Applicant: Yutaka Ida ,  Yoshikazu Yagi ,  Tsutomu Ieki ,  Hiroaki Tanaka ,  Osamu Chikagawa

Inventor： Yutaka Ida ,  Yoshikazu Yagi ,  Tsutomu Ieki ,  Hiroaki Tanaka ,  Osamu Chikagawa

IPC: H01P308

CPC classification number: H01P3/081 ,  H01P1/20363 ,  H01P1/20381 ,  H01P3/088 ,  H01P7/082 ,  H01P11/003 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/162 ,  H05K3/107 ,  H05K3/4092 ,  H05K2201/037 ,  H05K2201/09036 ,  H05K2201/098 ,  H05K2201/09981

Abstract: A microstrip line includes a strip conductor, a line electrode, and edge electrodes provided at the edges on both sides of the line electrode. The construction of the microstrip line greatly reduces the edge effect of the line electrode and decreases the conductor loss of the line electrode.

Abstract translation: 微带线包括带状导体，线电极和设置在线电极两侧边缘的边缘电极。 微带线的结构大大降低了线电极的边缘效应，并降低了线电极的导体损耗。

公开(公告)号：US20030188888A1

公开(公告)日：2003-10-09

申请号：US09808086

申请日：2001-03-13

Inventor： Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

IPC: H05K001/11 ,  H05K003/02

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 nullm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract translation: 多层印刷电路板形成有多个导体层，绝缘层整体层叠在一起，绝缘层中设置的非穿透通孔由导体层露出的底部，设置在通孔内部的镀层， 所述导体层之间的电连接，所述通孔形成为在通孔的内周到底面的连续区域的半径在20至100μm的范围内的轴向剖视图中的凹曲面的通孔，由此 在电镀镀层时发生的等电势面沿着连续区域弯曲，以统一电流密度，以使电镀层在厚​​度上均匀，而不会在连续区域变薄。

公开(公告)号：US06557250B2

公开(公告)日：2003-05-06

申请号：US10003296

申请日：2001-12-06

Applicant: Rudi W Opitz ,  Walter P Stuckmann

Inventor： Rudi W Opitz ,  Walter P Stuckmann

IPC: H05K336

CPC classification number: H01F17/0013 ,  H01F27/2804 ,  H01F41/041 ,  H05K1/165 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0759 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A multilayer printed board compound comprises at least two planely superposed printed boards, each of which having an electrically insulating mother board, electrically conductive circuit paths, which are provided on at least one side of the mother board, and recesses, which are defined laterally by the circuit paths and towards the mother board by the mother board; and at least one preimpregnated board, which is disposed between the printed boards for joining the printed boards; wherein the recesses, which are disposed between the mother boards of the respective printed boards, are filled substantially entirely with a synthetic resin paste; and wherein the at least two printed boards and the at least one preimpregnated board are joined by pressing.

Abstract translation: 多层印刷板化合物包括至少两个平面重叠的印刷电路板，每个印刷电路板具有电绝缘母板，设置在母板的至少一侧上的导电电路路径，以及凹槽，其横向由 电路通路和母板朝母板; 以及至少一个预浸渍板，其设置在用于接合印刷板的印刷板之间; 其中设置在各个印刷电路板的母板之间的凹部基本上用合成树脂浆料填充; 并且其中所述至少两个印刷板和所述至少一个预浸渍板通过压制而接合。

公开(公告)号：US20030015574A1

公开(公告)日：2003-01-23

申请号：US10214187

申请日：2002-08-08

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kouichi Teshima ,  Emiko Higashinakagawa ,  Shinji Arai

IPC: B23K035/12

CPC classification number: H05K3/3463 ,  B23K35/262 ,  H01L23/488 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/111 ,  H05K3/3421 ,  H05K2201/098 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T428/1266 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12792 ,  H01L2924/00

Abstract: Disclosed is a solder alloy in use for bonding electric or electronic parts, containing: 3 to 12% by weight of a zin component; and a tin component. The oxygen content of the solder alloy is reduced to 100 ppm or less. Using the solder alloy, a bonding portion is formed on the substrate and the electronic part is mounted thereon to obtain a substrate for mounting the electronic part and a substrate on which the electronic part is mounted. The bonding portion made of the above solder alloy can prevent migration.

Abstract translation: 公开了用于粘接电子或电子部件的焊料合金，其包含：3至12重量％的锌组分; 和锡组分。 焊料合金的氧含量降低到100ppm以下。 使用焊料合金，在基板上形成接合部，并且将电子部件安装在其上，以获得用于安装电子部件的基板和安装有电子部件的基板。 由上述焊料合金制成的接合部可以防止迁移。