公开(公告)号：US06268239B1

公开(公告)日：2001-07-31

申请号：US09552797

申请日：2000-04-20

Applicant: Renya Ikeda

Inventor： Renya Ikeda

IPC: H01L2144

CPC classification number: H05K1/0204 ,  H01L23/3677 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/15321 ,  H01L2924/3011 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/09054 ,  H05K2201/10477 ,  H05K2201/10674

Abstract: A semiconductor chip is mounted on a small-size circuit board having a hole, in flip-chip mounting. The small-size circuit board is connected to a large-size circuit board so that the semiconductor chip will be placed between the small-size circuit board and the large-size circuit board and there will be a clearance between the semiconductor chip and the large-size circuit board. A heat sink is provided with a convex part for being inserted into the hole of the small-size circuit board to be thermally connected to the surface of the semiconductor chip through a thermal conduction material which is sandwiched between the convex part and the semiconductor chip. The heat sink is fixed to the large-size circuit board by means of fixation screws etc. so that the semiconductor chip and the small-size circuit board will be placed between the heat sink and the large-size circuit board. The fixation load for fixing the heat sink to the large-size circuit board is not applied to the semiconductor chip at all and thereby damages to the semiconductor chip due to the fixation is eliminated. The surface of the semiconductor chip is almost directly connected to the convex part of the heat sink via the thermal conduction material, therefore, the cooling of the semiconductor chip in flip-chip mounting is executed with high cooling efficiency.

Abstract translation: 在倒装芯片安装中，半导体芯片安装在具有孔的小尺寸电路板上。 小尺寸电路板连接到大尺寸电路板，使得半导体芯片将放置在小尺寸电路板和大尺寸电路板之间，并且半导体芯片与大尺寸电路板之间将具有间隙 尺寸电路板。 散热器设置有用于插入到小型电路板的孔中的凸部，以通过夹在凸部和半导体芯片之间的导热材料热连接到半导体芯片的表面。 散热器通过固定螺钉等固定在大尺寸电路板上，使半导体芯片和小尺寸电路板放置在散热片和大尺寸电路板之间。 用于将散热器固定到大尺寸电路板的固定载荷根本不施加到半导体芯片，由此消除了由于固定而对半导体芯片的损坏。 半导体芯片的表面通过导热材料几乎直接连接到散热器的凸部，因此以高冷却效率执行倒装芯片安装中的半导体芯片的冷却。

公开(公告)号：US06265766B1

公开(公告)日：2001-07-24

申请号：US09483483

申请日：2000-01-14

Applicant: Walter L. Moden

Inventor： Walter L. Moden

IPC: H01L2302

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/141 ,  H05K3/328 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10477 ,  H05K2203/0415 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

公开(公告)号：US6125026A

公开(公告)日：2000-09-26

申请号：US343908

申请日：1999-06-30

Applicant: Mark A. De Samber ,  Gerjan F. A. Van De Walle

Inventor： Mark A. De Samber ,  Gerjan F. A. Van De Walle

IPC: H05K1/18 ,  H01G4/30 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K7/02

CPC classification number: H05K3/3442 ,  H01G4/306 ,  H01L23/49805 ,  H01L2224/16 ,  H01L2224/32225 ,  H05K2201/10477 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49787 ,  Y10T29/49789

Abstract: The invention relates to an electric component (surface mountable component) which can be mounted on the surface of a printed circuit board. Such a component includes a thin, electroconductive layer or stack of layers which is provided with end contacts and arranged on a support of an electrically insulating material. In accordance with the invention, the dimension of the layer or stack of layers in at least one direction parallel to the surface of the support is smaller than the dimension of the support in the direction, while leaving portions of the surface of the support clear on at least two sides of the layer or stack of layers, and end contacts for the layer or stack of layers are situated on the surface portions of the support which are free of this layer or stack of layers, the thickness of the end contacts being larger than the thickness of the layer or stack of layers.

Abstract translation: 本发明涉及一种可安装在印刷电路板表面上的电气部件（表面安装部件）。 这种部件包括薄的导电层或层叠体，其设置有末端触点并且布置在电绝缘材料的支撑件上。 根据本发明，在平行于支撑件的表面的至少一个方向上的层或层的尺寸小于支撑件在该方向上的尺寸，同时使支撑体的表面的一部分清除 层或层叠层的至少两侧和层或层叠层的端触点位于不含该层或层叠层的支撑体的表面部分上，端部触点的厚度较大 比层或层叠层的厚度。

公开(公告)号：US6117300A

公开(公告)日：2000-09-12

申请号：US113043

申请日：1998-07-09

Applicant: Derek Carbin ,  Wendy A. Herrick

Inventor： Derek Carbin ,  Wendy A. Herrick

IPC: B32B15/08 ,  H05K3/00 ,  H05K3/02 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46 ,  C25D5/02

CPC classification number: H05K3/025 ,  H05K3/108 ,  H05K3/384 ,  H05K2201/0317 ,  H05K2201/0344 ,  H05K2201/0355 ,  H05K2201/10477 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/0726 ,  H05K3/4652 ,  Y10T29/49155

Abstract: A method of forming circuit lines on a substrate by applying a roughened conductive metal layer using a copper foil carrier. The copper foil is etched away, leaving the roughened conductive metal embedded in the surface of the substrate. The conductive metal may be treated to remove an oxide layer. A photoresist may also be applied over the treated conductive metal layer to define a fine line circuit pattern. The photoresist defining the fine line circuit pattern is then removed to expose trenches in accordance with the desired circuit pattern. Copper is applied into the trenches over the exposed conductive metal, and the remaining photoresist, and conductive metal underlying the remaining photoresist, is removed to finish the fine line circuit pattern.

Abstract translation: 通过使用铜箔载体涂布粗糙化的导电金属层，在基板上形成电路线的方法。 蚀刻掉铜箔，留下粗糙的导电金属嵌入衬底的表面。 可以处理导电金属以除去氧化物层。 还可以在经处理的导电金属层上施加光致抗蚀剂以限定细线电路图案。 然后去除限定细线电路图案的光致抗蚀剂，以根据期望的电路图案露出沟槽。 将铜施加到暴露的导电金属上的沟槽中，并且剩余的光致抗蚀剂和剩余光致抗蚀剂下面的导电金属被去除以完成细线电路图案。

公开(公告)号：US5952719A

公开(公告)日：1999-09-14

申请号：US891446

申请日：1997-07-10

Applicant: Peter W. Robinson ,  Deepak Mahulikar ,  Paul R. Hoffman

Inventor： Peter W. Robinson ,  Deepak Mahulikar ,  Paul R. Hoffman

IPC: H01L23/06 ,  H01L23/08 ,  H01L23/13 ,  H01L23/14 ,  H01L23/24 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H05K1/02 ,  H05K3/30 ,  H01L23/48

CPC classification number: H01L23/13 ,  H01L23/142 ,  H01L23/24 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/49816 ,  H01L24/32 ,  H05K3/305 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K1/0271 ,  H05K2201/10477 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/613

Abstract: The bending of a ball grid array electronic package having a metallic base is reduced minimizing stresses applied to the innermost row of solder balls when the package base is cyclically heated and cooled. Reducing the stresses applied to the solder balls increases the number of thermal cycles before solder ball fracture causes device failure. Among the means disclosed to reduce the bending moment are a bimetallic composite base, an integral stiffener, a centrally disposed cover bonded to an external structure and a package base with a stress accommodating depressed portion.

Abstract translation: 当包装基底被循环加热和冷却时，具有金属基底的球栅阵列电子封装的弯曲减小了最小化施加到最内排焊球的应力。 减少施加到焊球上的应力增加了焊球破裂导致装置故障之前的热循环次数。 公开的用于减小弯矩的手段是双金属复合基座，整体加强件，结合到外部结构的中心布置的盖子和具有应力容纳凹陷部分的封装基座。

公开(公告)号：US5936302A

公开(公告)日：1999-08-10

申请号：US845655

申请日：1997-04-25

Applicant: David V. Pedersen ,  Michael G. Finley ,  Kenneth M. Sautter

Inventor： David V. Pedersen ,  Michael G. Finley ,  Kenneth M. Sautter

IPC: H01L25/00 ,  H01L21/60 ,  H01L21/66 ,  H01L21/98 ,  H01L23/373 ,  H01L23/482 ,  H01L23/485 ,  H01L23/52 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06 ,  H01R4/04 ,  H01R29/00 ,  H05K3/30 ,  H05K3/32 ,  H05K7/02 ,  H01L23/58

CPC classification number: H01L23/3737 ,  H01L22/22 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01R29/00 ,  H01R4/04 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L29/0657 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613

Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack. This is accomplished by connecting a set of metal switches between all the die and each of the control lines and by dispensing a conductive epoxy whisker between the control line for the defective die and the metal switch of the replacement die. When a subsequent attempt is made to address the defective die in the stack, the replacement die is accessed instead.

Abstract translation: 本发明是用于对一段片段进行编程的方法和装置，其中每个片段包括通过在每个片段的表面上图案化的金属互连而互连的多个片。 一旦片段被布置成堆叠，堆叠被连接到外部电路，并且每个片段通过控制线寻址。 导线上的导电保险丝用作控制线和管芯之间的接口。 通过以预定模式打开段上的导电熔丝，以便将控制线路由到每个段，使得段被唯一寻址，在每个段执行段级编程。 在段级编程之后，执行电路板编程，使得在堆栈中发现的任何有缺陷的管芯在逻辑上被堆叠中的替换管芯替代。 这通过在所有管芯和每个控制线之间连接一组金属开关并且通过在有缺陷管芯的控制线和更换管芯的金属开关之间分配导电环氧树脂晶须来实现。 当随后尝试解决堆叠中的有缺陷的裸片时，改为替换裸片。

公开(公告)号：US5837566A

公开(公告)日：1998-11-17

申请号：US847309

申请日：1997-04-24

Applicant: David V. Pedersen ,  Michael G. Finley ,  Kenneth M. Sautter

Inventor： David V. Pedersen ,  Michael G. Finley ,  Kenneth M. Sautter

IPC: H01L25/00 ,  H01L21/60 ,  H01L21/98 ,  H01L23/373 ,  H01L23/482 ,  H01L23/485 ,  H01L23/52 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06 ,  H01R4/04 ,  H01R29/00 ,  H05K3/30 ,  H05K3/32 ,  H05K7/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/81 ,  H01L23/3737 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01R29/00 ,  H01R4/04 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L29/0657 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613

Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.

Abstract translation: 一种用于垂直互连硅片段叠层的方法和装置。 每个段在半导体晶片上包括多个相邻的管芯。 使用一个或多个金属互连层在片段上互连多个管芯，该金属互连件延伸到段的全部四个侧面，以提供用于外部电连接点的边缘焊盘。 在芯片互连后，使用斜切切割从晶片的背面切割每个片段，以在每个片段上提供四个向内倾斜的边缘壁。 在从晶片切割片段之后，将片段放置在彼此的顶部以形成叠片。 堆叠中的垂直相邻段通过将导电环氧树脂施加到堆叠的所有四个侧面而电互连。 堆叠中的每个段的向内倾斜的边缘壁提供凹部，其允许导电环氧树脂在片段堆叠之后接近每个片段上的边缘接合焊盘和侧向电路。 然后将电互连段的堆叠安装在电路板的表面下方，并通过在堆叠顶部的接合焊盘和电路板之间施加迹线的导电环氧树脂电连接到电路板上的电路。

公开(公告)号：US5784248A

公开(公告)日：1998-07-21

申请号：US832910

申请日：1997-04-04

Applicant: Tomohiro Tomiyasu ,  Yasuo Kanetake

Inventor： Tomohiro Tomiyasu ,  Yasuo Kanetake

IPC: H01G2/06 ,  H01G2/04 ,  H01G9/00 ,  H01G9/004 ,  H01G9/012 ,  H01G9/04 ,  H01G9/052 ,  H01G9/12 ,  H01L21/60 ,  H05K1/02 ,  H05K3/28 ,  H05K3/30 ,  H05K3/32

CPC classification number: H01G2/04 ,  H01G9/012 ,  H01L24/48 ,  H05K1/0201 ,  H05K3/328 ,  H01L2224/05599 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49175 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/0263 ,  H05K2201/10181 ,  H05K2201/10287 ,  H05K2201/10477 ,  H05K2203/049 ,  H05K3/284 ,  H05K3/303 ,  H05K3/305 ,  H05K3/321

Abstract: A method and assembly are provided for mounting a solid electrolytic capacitor onto a printed circuit board including an anode pad and a cathode pad. The capacitor includes a capacitor element which has an anode and a cathode electrically separated by a dielectric substance. The cathode includes an outer cathode terminal layer formed over the element. The method includes the steps of removing a part of the cathode terminal layer to expose a flat anode terminal surface, attaching the element to the printed circuit board for bringing the cathode terminal layer into electrical connection with the cathode pad, electrically connecting the flat anode terminal surface to the anode pad via a metal wire, and enclosing the element in a resin member for protection.

Abstract translation: 提供了一种将固体电解电容器安装到包括阳极焊盘和阴极焊盘的印刷电路板上的方法和组件。 该电容器包括电容器元件，其具有由电介质物质电隔离的阳极和阴极。 阴极包括形成在元件上的外阴极端子层。 该方法包括以下步骤：去除阴极端子层的一部分以暴露平坦的阳极端子表面，将该元件附着到印刷电路板上，以使阴极端子层与阴极焊盘电连接，将平坦的阳极端子 通过金属线将其表面连接到阳极焊盘，并将元件封装在树脂构件中用于保护。

公开(公告)号：US5728247A

公开(公告)日：1998-03-17

申请号：US620950

申请日：1996-03-25

Applicant: Gunther Bustrich ,  Lars Erik Pontus Lundstrom

Inventor： Gunther Bustrich ,  Lars Erik Pontus Lundstrom

IPC: H01L21/60 ,  H05K3/32 ,  B32B31/04 ,  H01L23/48

CPC classification number: H01L24/85 ,  H01L24/73 ,  H01L24/81 ,  H01L24/86 ,  H05K3/328 ,  H01L2224/48091 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2203/049 ,  Y10T156/1002 ,  Y10T156/1062 ,  Y10T29/4913 ,  Y10T29/49147

Abstract: The present invention provides a method when using chips for tape automated bonding, or TAB structures, whereby a demand of having particular cutting and bending tools for each type of TAB structure as well as a particular thermod will no longer be necessary for the mounting of the TAB structures in a final circuit configuration. The terminal leads of a TAB structure are cut along the four sides by means of a particular cutting tool. Furthermore either the chip is glued to the substrate and/or the remaining portions of the cut terminal leads of the TAB structure are glued to the substrate, whereby if desirable intermediate shielding or dielectric layers simply may be arranged, whereupon all terminals are wire-bonded to the substrate according to prior art. TAB structures hereby may conveniently be used also for low levels of production without a raised investment cost for particular different tools for the respective chips.

Abstract translation: 本发明提供了一种使用用于胶带自动粘合的芯片或TAB结构的方法，由此，对于每种类型的TAB结构以及特定的热电偶，具有特定切割和弯曲工具的需求将不再需要用于安装 最终电路配置中的TAB结构。 TAB结构的端子引线通过特定的切削工具沿着四边切割。 此外，芯片被粘合到基板上，和/或TAB结构的切割端子引线的剩余部分粘合到基板上，由此，如果可以简单地布置希望的中间屏蔽或电介质层，则所有端子都被引线键合 到根据现有技术的基底。 因此，TAB结构可以方便地用于低水平的生产，而不需要为相应芯片的特定不同工具的投资成本提​​高。

公开(公告)号：US5719440A

公开(公告)日：1998-02-17

申请号：US574662

申请日：1995-12-19

Applicant: Walter L. Moden

Inventor： Walter L. Moden

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H01L28/48

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/75 ,  H01L24/85 ,  H05K3/328 ,  H05K3/3436 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10477 ,  H05K2203/0415 ,  H05K2203/049 ,  H05K3/368 ,  Y02P70/613

Abstract: A board connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract translation: 将裸半导体管芯与接合焊盘装置连接的板，其不符合具有特定或标准的引脚输出，连接器焊盘或引线放置布置的主印刷电路板。 板包括印刷电路板，其包括第一元件，例如用于在基板和母板之间进行电接触的微小焊球，引脚或接合线，以及第二元件，例如微小的焊球，引脚或接合线 用于在半导体管芯和电路板之间进行电接触。 电路板具有用于电路板/主板电接触元件之间的电气通信的电路迹线以及半导体裸片板电接触元件。