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公开(公告)号：US10804604B2
公开(公告)日：2020-10-13
申请号：US16372569
申请日：2019-04-02
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling
Abstract: A system comprises a plurality of antenna elements, a transmitter circuit, and first and second receiver circuits. The transmitter is operable to: transmit, via a first antenna element, a series of signals having a calibration component and each of the signals being generated with a different configuration of the transmitter circuit; and select a configuration for a future transmission based on a signal metric. The first receiver circuit is operable to: receive the signal via a second antenna element; and detect the calibration component in the signal to generate a first calibration signal. The second receiver circuit is operable to: receive the signal via a third antenna element; detect the calibration component in the signal to generate a second calibration signal; combine the first and second calibration signals to generate a combined calibration signal; and generate the signal metric based on the combined calibration signal.
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公开(公告)号：US10705209B2
公开(公告)日：2020-07-07
申请号：US16189705
申请日：2018-11-13
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling
IPC: G01S13/931 , G01S7/28 , G01S13/02 , G01S13/42 , G01S13/87 , G01S13/89 , G01S13/60 , G01S13/86 , G01S7/00 , G01S7/40 , H01Q1/32 , H01Q3/24
Abstract: A radar transmitter comprises orthogonal frequency division multiplexing (OFDM) symbol generation circuitry, windowing circuitry, and control circuitry. The OFDM symbol generation circuitry is operable to modulate data onto a plurality of subcarriers to generate a plurality of OFDM symbols. The windowing circuitry is configurable to support a plurality of windowing functions. The control circuitry is operable to analyze returns from a previous transmission of the radar transmitter to determine characteristics of the environment into which the previous transmission was transmitted. The control circuitry is operable to select which one of the plurality of windowing functions the windowing circuitry is to apply to each of the plurality of OFDM symbols based on the characteristics of the environment. A first one of the windowing functions may correspond to a first radiation pattern and the second one of the windowing functions may correspond to a second radiation pattern.
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公开(公告)号：US10658763B2
公开(公告)日：2020-05-19
申请号：US16259177
申请日：2019-01-28
Applicant: Maxlinear, Inc.
Inventor： Timothy Gallagher , Curtis Ling
Abstract: An array based communications system may comprise a plurality of element processors. Each element processor may comprise a combining circuit, a crest factor circuit, and a phase shifter circuit. The combining circuit may produce a weighted sum of a plurality of digital datastreams. The crest factor circuit may be operable to determine whether the weighted sum has a power above or below a power threshold. If the power is above the power threshold, the crest factor circuit is operable to reduce the power. If the power is below the power threshold, the crest factor circuit is operable to increase the power. The phase shifter circuit may introduce a phase shift to out-of-band components of the weighted sum according to the power increase or the power decrease by the crest factor circuit.
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公开(公告)号：US10651806B2
公开(公告)日：2020-05-12
申请号：US16268002
申请日：2019-02-05
Applicant: Maxlinear, Inc.
Inventor： Abhishek Jajoo , Vamsi Paidi
Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.
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公开(公告)号：US10574261B2
公开(公告)日：2020-02-25
申请号：US15997183
申请日：2018-06-04
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Jining Duan
Abstract: A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.
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Patent Agency Ranking
公开(公告)号：US20200052771A1
公开(公告)日：2020-02-13
申请号：US16657725
申请日：2019-10-18
Applicant: MaxLinear, Inc.
Inventor： Curtis Ling
IPC: H04B7/08 , H04B7/06 , H04B7/0408
Abstract: Systems and methods are provided for utilizing antenna arrays with digital beamforming. An array-based system may have a plurality of antenna elements arranged in a two-dimensional array, and a plurality of transceiver chips configured for handling transmission and reception of radio frequency (RF) signals via the plurality of antenna elements. A number of transceiver chips in the plurality of transceiver chips may be less than a number of antenna elements in the plurality of antenna elements. The plurality of transceiver chips is configured to control operation of the plurality of antenna elements such that digital or hybrid beamforming is enabled during the transmission and reception of RF signals via the plurality of antenna elements.
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公开(公告)号：US20200021250A1
公开(公告)日：2020-01-16
申请号：US16584423
申请日：2019-09-26
Applicant: MaxLinear, Inc.
Inventor： Prasun Kali Bhattacharyya , Abhishek Ghosh , Prasenjit Bhowmik
Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.
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公开(公告)号：US20200007307A9
公开(公告)日：2020-01-02
申请号：US14457100
申请日：2014-08-11
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Timothy Gallagher
IPC: H04L7/00
Abstract: Methods and systems for cross-protocol time synchronization may comprise, for example, in a premises-based network, receiving a signal that conforms to a data over cable service interface specification (DOCSIS) communications protocol. A global time of day (GTOD) clock may be extracted from the received signal. Communication on the premises-based network in accordance with a multimedia over cable alliance (MoCA) communications protocol may be synchronized based at least in part on the extracted GTOD clock. Communication in a third communications protocol may be synchronized, wherein the third communications protocol may include a home phoneline networking alliance (HPNA) standard, an IEEE 802.11x standard, and a non-public wireless network protocol. The extracted GTOD clock may comprise a GPS clock, GLONASS clock, and a Galileo clock. A second signal for extracting a GTOD may be received, such as a satellite signal, and may conform to a low Earth orbit satellite signal protocol.
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公开(公告)号：US20190341927A1
公开(公告)日：2019-11-07
申请号：US16403812
申请日：2019-05-06
Applicant: Maxlinear, Inc.
Inventor： Rakesh Kumar Palani , Suman Sah
Abstract: A system comprises an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit comprises a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.
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公开(公告)号：US20190341892A1
公开(公告)日：2019-11-07
申请号：US16400483
申请日：2019-05-01
Applicant: Maxlinear, Inc.
Inventor： Anand Mohan Pappu , Ranjit Kumar Guntreddi , Madhusudan Govindarajan , Pranjal Pandey , Prasenjit Bhowmik
Abstract: A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.
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