公开(公告)号：US09666337B2

公开(公告)日：2017-05-30

申请号：US14486775

申请日：2014-09-15

Applicant: Sinovia Technologies

Inventor： Whitney Gaynor ,  George Burkhard

IPC: H01B13/00 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16 ,  G06F3/041 ,  H01B1/22 ,  H01L51/44 ,  B82Y20/00

CPC classification number: G06F3/041 ,  B05D3/007 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F7/0002 ,  G03F7/0047 ,  G03F7/038 ,  G03F7/0388 ,  G03F7/161 ,  G06F3/044 ,  G06F2203/04103 ,  H01B1/22 ,  H01B5/14 ,  H01B13/0013 ,  H01L51/444 ,  H01L51/5203 ,  H05K1/0271 ,  H05K1/0274 ,  H05K1/036 ,  H05K1/09 ,  H05K3/103 ,  H05K2201/0108 ,  H05K2201/0137 ,  H05K2203/10 ,  Y10T428/24355 ,  Y10T442/188 ,  Y10T442/191

Abstract: A composite conductive film is provided that includes a layer of cross-linked polymer having a surface and an inorganic mesh comprising a plurality of nanowires of an inorganic material. The nanowires are, in isolated form, characterized by a first conductivity stability temperature. Further, the plurality of nanowires is embedded within at least a region of the layer of cross-linked polymer, where the region is continuous from the surface of the layer of cross-linked polymer. The layer of cross-linked polymer and the inorganic mesh are arranged to form the composite conductive film having a second conductivity stability temperature that is greater than the first conductivity stability temperature.

公开(公告)号：US09617385B2

公开(公告)日：2017-04-11

申请号：US14885759

申请日：2015-10-16

Applicant: International Business Machines Corporation

Inventor： Dylan J. Boday ,  Jeannette M. Garcia ,  James L. Hedrick ,  Rudy J. Wojtecki

IPC: C08G8/16 ,  C08G73/06 ,  H01B1/12 ,  C08J5/24 ,  D06M15/37 ,  H01B13/00 ,  H01L23/522

CPC classification number: C08G73/0644 ,  C08G12/06 ,  C08G73/0638 ,  C08J5/24 ,  C08J2379/04 ,  D06M15/37 ,  H01B1/128 ,  H01B13/0026 ,  H01L23/5226 ,  H05K1/0346 ,  H05K2201/0137

Abstract: Low dielectric constant (low-k) polyhemiaminal (PHA) and polyhexahydrotriazine (PHT) materials with cyclic aliphatic ring structures are described. The materials are formed by a method that includes heating a mixture comprising amines and paraformaldehyde. The reaction mixtures may be used to form low-k PHT prepregs, composites and dielectrics used in integrated circuits.

公开(公告)号：US09491853B2

公开(公告)日：2016-11-08

申请号：US14486815

申请日：2014-09-15

Applicant: Sinovia Technologies

Inventor： Whitney Gaynor ,  George Burkhard

IPC: H05K1/09 ,  H05K1/02 ,  H05K1/03 ,  H05K3/10 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16 ,  H01B1/22 ,  G06F3/044 ,  H01L51/44 ,  H01L51/52 ,  G03F7/038 ,  B82Y20/00

CPC classification number: G06F3/041 ,  B05D3/007 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F7/0002 ,  G03F7/0047 ,  G03F7/038 ,  G03F7/0388 ,  G03F7/161 ,  G06F3/044 ,  G06F2203/04103 ,  H01B1/22 ,  H01B5/14 ,  H01B13/0013 ,  H01L51/444 ,  H01L51/5203 ,  H05K1/0271 ,  H05K1/0274 ,  H05K1/036 ,  H05K1/09 ,  H05K3/103 ,  H05K2201/0108 ,  H05K2201/0137 ,  H05K2203/10 ,  Y10T428/24355 ,  Y10T442/188 ,  Y10T442/191

Abstract: A composite conductive film is provided that includes a layer of cross-linked polymer having a surface and an inorganic mesh comprising a plurality of inorganic nanowires. The plurality of inorganic nanowires is embedded throughout at least a region of the layer of cross-linked polymer. The region is continuous from the surface of the layer of cross-linked polymer. The layer of cross-linked polymer and the inorganic mesh are arranged to form the composite conductive film. The composite conductive film has a pencil test hardness in a range of 2H to 9H.

Abstract translation: 提供一种复合导电膜，其包括具有表面的交联聚合物层和包含多个无机纳米线的无机网。 多个无机纳米线被嵌入到交联聚合物层的至少一个区域内。 该区域从交联聚合物层的表面连续。 布置交联聚合物层和无机网以形成复合导电膜。 复合导电膜的铅笔测试硬度在2H〜9H的范围内。

公开(公告)号：US09408295B2

公开(公告)日：2016-08-02

申请号：US14701792

申请日：2015-05-01

Applicant: NGK Insulators, Ltd.

Inventor： Shinsuke Yano ,  Makoto Tani ,  Hirokazu Nakanishi

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K1/02 ,  H01L33/62 ,  H01L33/64 ,  H05K1/05

CPC classification number: H05K1/0207 ,  H01L33/62 ,  H01L33/641 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/16245 ,  H01L2933/0066 ,  H05K1/0204 ,  H05K1/0209 ,  H05K1/053 ,  H05K2201/0137 ,  H05K2201/062 ,  H05K2201/068 ,  H05K2201/10106 ,  H05K2201/10416 ,  H05K2203/1126

Abstract: A substrate for a light-emitting diode comprising a metal base with a thickness of a predetermined value or more is constituted so that the thickness of a top conductor for an electrical connection with a light-emitting diode (LED) in a predetermined range falls within a predetermined range and the thickness of an insulation layer which electrically insulates the metal base and the top conductor and the thickness of the top conductor meet a predetermined relation. Thereby, a substrate for a light-emitting diode which can show a high heat dissipation capacity by achieving a low thermal resistance as the total thermal resistance of the whole substrate without reducing insulation reliability and high-humidity reliability of the substrate is provided.

Abstract translation: 包括具有预定值或更大厚度的金属基底的发光二极管的基板被构成为使得与预定范围内的发光二极管（LED）的电连接的顶部导体的厚度在其内 电绝缘金属基底和顶部导体的绝缘层和顶部导体的厚度的预定范围和厚度满足预定关系。 因此，提供了一种通过实现低热阻作为整个基板的总热阻而可以显示出高散热能力而不降低基板的绝缘可靠性和高湿度可靠性的发光二极管的基板。

公开(公告)号：US20160163611A1

公开(公告)日：2016-06-09

申请号：US14558864

申请日：2014-12-03

Applicant: International Business Machines Corporation

Inventor： Edmund Blackshear ,  Shidong Li

IPC: H01L23/14 ,  B32B15/092 ,  B32B27/06 ,  H01L23/13 ,  B32B37/14 ,  B32B38/00 ,  H01L21/48 ,  B32B3/26 ,  B32B27/38

CPC classification number: H01L23/49833 ,  B32B3/08 ,  B32B3/10 ,  B32B3/266 ,  B32B5/16 ,  B32B7/02 ,  B32B15/092 ,  B32B15/20 ,  B32B27/04 ,  B32B27/20 ,  B32B27/38 ,  B32B37/02 ,  B32B37/182 ,  B32B38/0004 ,  B32B2250/05 ,  B32B2250/40 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2264/10 ,  B32B2264/101 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/734 ,  B32B2363/00 ,  B32B2457/00 ,  B32B2457/14 ,  H01L21/4803 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/0137 ,  H05K2201/0191 ,  H05K2201/0206 ,  H05K2201/0209 ,  H05K2201/09136 ,  H05K2201/09209 ,  H05K2201/0929 ,  H05K2203/06 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24298 ,  Y10T428/24314 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/25 ,  H01L2924/00

Abstract: A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.

Abstract translation: 一种用于接收半导体芯片的层叠基板。 包括层叠层叠以形成层压基板的层压层，每个层压层包括芯，其包括颗粒填充的环氧树脂和芯上的金属层。 至少一个层压层具有穿过金属层的径向切口，径向切口从至少一层压层的周边延伸到至少一层压层的中心。 径向切割仅穿过金属层，并且不切穿芯。

公开(公告)号：US20150373853A1

公开(公告)日：2015-12-24

申请号：US14312222

申请日：2014-06-23

Applicant: ILLINOIS TOOL WORKS, INC.

Inventor： Hongchuan LIAO ,  Chris BENSON ,  Yong Liang ,  Tom Carlson

IPC: H05K1/18

CPC classification number: H05K1/185 ,  B32B27/08 ,  B32B27/20 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B27/365 ,  B32B2250/24 ,  B32B2250/40 ,  B32B2262/106 ,  B32B2264/02 ,  B32B2264/102 ,  B32B2264/105 ,  B32B2264/107 ,  B32B2264/108 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/212 ,  B32B2307/302 ,  B32B2457/04 ,  H05K2201/0137 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0183 ,  Y10T428/31507 ,  Y10T428/31681 ,  Y10T428/31692 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31728 ,  Y10T428/31736 ,  Y10T428/31757 ,  Y10T428/31786 ,  Y10T428/31797 ,  Y10T428/31913

Abstract: The present invention provides an insulation film and a method for making the insulation film, comprising a film upper layer and a film lower layer, wherein both of the film upper layer and film lower layer are made of a heat conduction plastics material, the heat conduction plastics material contains a heat conduction additive; and a film intermediate layer located between the film upper layer and the film lower layer. The film intermediate layer is made of a heat conduction plastics material, and the heat conduction plastics material contains a conductive additive An upper surface of the film intermediate layer is bound together with a lower surface of the film upper layer, and a lower surface of the film intermediate layer is bound together with an upper surface of the film lower layer.

Abstract translation: 本发明提供一种绝缘膜和制造绝缘膜的方法，包括膜上层和膜下层，其中膜上层和膜下层都由导热塑料材料制成，热传导 塑料材料含有导热添加剂; 以及位于膜上层和膜下层之间的膜中间层。 膜中间层由导热塑料材料制成，导热塑料材料含有导电添加剂膜中间层的上表面与膜上层的下表面结合在一起， 膜中间层与膜下层的上表面结合在一起。

公开(公告)号：US20150163921A1

公开(公告)日：2015-06-11

申请号：US14102676

申请日：2013-12-11

Applicant: Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, JR. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Teles Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, JR. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Teles Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  G06F1/16 ,  H05K13/04

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

Abstract translation: 本公开一般涉及用于制造柔性微电子组件的装置，系统和方法。 在一个实例中，聚合物模制在微电子部件上，聚合物模具在模制之后呈现基本刚性的状态。 相对于微电子部件和聚合物模具形成布线层，布线层包括电耦合到微电子部件的迹线。 输入被施加到聚合物模具，聚合物模具在施加输入时从基本刚性状态转变到基本上柔性的状态。

公开(公告)号：US20150107885A1

公开(公告)日：2015-04-23

申请号：US14142036

申请日：2013-12-27

Applicant: Applied Materials, Inc.

Inventor： Neil MORRISON ,  Thomas DEPPISCH ,  Hans-Georg LOTZ

IPC: G06F3/0354 ,  H05K1/02 ,  H05K1/03 ,  G06F3/044

CPC classification number: G06F3/03547 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0274 ,  H05K1/0306 ,  H05K2201/0137 ,  H05K2201/0145

Abstract: A layer stack for a touch panel is described. The layer stack includes a substrate including a polymer for depositing one or more layers on the substrate; a patterned transparent conductive oxide (TCO) layer provided over the substrate, which comprises areas of TCO and gaps between the areas of TCO; a first dielectric material provided in the gaps of the patterned TCO layer and a dielectric layer being deposited directly on the TCO areas of the TCO layer and directly on the first dielectric material. Further, a touch panel including a layer stack and a method for forming a layer stack for a touch panel is described.

Abstract translation: 描述了用于触摸面板的层叠体。 所述层叠层包括基板，所述基板包括用于在所述基板上沉积一层或多层的聚合物; 设置在衬底上的图案化透明导电氧化物（TCO）层，其包括TCO区域和TCO区域之间的间隙; 设置在图案化TCO层的间隙中的第一电介质材料和直接沉积在TCO层的TCO区上且直接沉积在第一介电材料上的电介质层。 此外，描述了包括层堆叠的触摸面板和用于形成用于触摸面板的层叠体的方法。

公开(公告)号：US20110290540A1

公开(公告)日：2011-12-01

申请号：US13064986

申请日：2011-04-29

Applicant: Hyungmi Jung ,  Jaechoon Cho ,  Choonkeun Lee ,  Taesung Jeong ,  Seungeun Lee ,  Jinsun Park ,  Yeena Shin

Inventor： Hyungmi Jung ,  Jaechoon Cho ,  Choonkeun Lee ,  Taesung Jeong ,  Seungeun Lee ,  Jinsun Park ,  Yeena Shin

IPC: H05K1/03 ,  B32B38/00 ,  H05K1/02 ,  B32B38/10 ,  H05K3/30 ,  B32B37/02 ,  B32B38/08

CPC classification number: H05K1/183 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K1/0353 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0023 ,  H05K3/30 ,  H05K3/4676 ,  H05K2201/0137 ,  H05K2201/0209 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Disclosed herein are an embedded printed circuit board and a method of manufacturing the same. The embedded printed circuit board includes: an insulating layer on which a cavity is formed; a chip mounted on the cavity; and a circuit layer formed on the insulating layer, wherein the insulating layer is made of photosensitive compositions including photosensitive monomer and photoinitiator. As a result, the cavity can be formed by selectively using only the insulating layer, thereby making it possible to secure a degree of freedom in the design of the embedded printed circuit board.

Abstract translation: 本文公开了一种嵌入式印刷电路板及其制造方法。 嵌入式印刷电路板包括：形成空腔的绝缘层; 安装在腔体上的芯片; 以及形成在所述绝缘层上的电路层，其中所述绝缘层由包括光敏单体和光引发剂的感光组合物制成。 结果，可以通过仅选择性地使用绝缘层来形成空腔，从而可以确保嵌入式印刷电路板的设计的自由度。