公开(公告)号：USRE29784E

公开(公告)日：1978-09-26

申请号：US483972

申请日：1974-06-28

Applicant: Donald H. Chadwick ,  Ruben T. Apodaca

Inventor： Donald H. Chadwick ,  Ruben T. Apodaca

IPC: C23C18/16 ,  H05K1/05 ,  H05K1/09 ,  H05K3/06 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K3/44

CPC classification number: H05K1/09 ,  C23C18/1653 ,  H05K1/056 ,  H05K3/381 ,  H05K2201/0209 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2203/025 ,  H05K2203/0723 ,  H05K2203/1105 ,  H05K3/062 ,  H05K3/181 ,  H05K3/426 ,  H05K3/445

Abstract: A metal core printed circuit board which includes multiple layers of synthetic plastic resin material on a sheet of metal, and wherein the surface of the plastic material is of such character that it provides an acceptable bond on which are built up sundry layers of different metals, the innermost layer on the plastic surface and the other layers positioned one upon another, ultimately comprising a built up circuit pattern, and wherein areas intermediate the circuit pattern comprise an exposed surface of the resin material.

公开(公告)号：USB319339I5

公开(公告)日：1975-01-28

申请号：US31933972

申请日：1972-12-29

IPC: H05K3/00 ,  C23F1/00 ,  G03F1/54 ,  G03F1/68 ,  H01L21/027 ,  H05K1/03 ,  H05K3/10

CPC classification number: G03F1/54 ,  G03F1/50 ,  H05K1/0306 ,  H05K3/108 ,  H05K2201/0108 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T428/24917 ,  Y10T428/24926

公开(公告)号：US3748109A

公开(公告)日：1973-07-24

申请号：US3748109D

申请日：1971-06-11

Applicant: HOOKER CHEMICAL CORP

Inventor： LEE S

IPC: C01B25/06 ,  C23C18/16 ,  C23C18/20 ,  D06Q1/04 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  C23B5/48 ,  B23P3/00 ,  C23B5/60

CPC classification number: H05K3/38 ,  C01B25/06 ,  C23C18/1605 ,  C23C18/2086 ,  D06Q1/04 ,  H05K3/108 ,  H05K3/181 ,  H05K3/184 ,  H05K3/188 ,  H05K2201/0344 ,  H05K2201/0347 ,  Y10T428/24917 ,  Y10T428/3167

Abstract: PRINTED CIRCUITS, INTEGRATED CIRCUITS, RESISTORS, THERMOCOUPLES, CONDENSERS, SUPERCONDUCTORS, ELECTROFORMED MATERIALS, AND THE LIKE ARE PRODUCED BY PROVIDING A PLASTIC OR SUBSTANTIALLY NON-METALLIC SUBSTRATE WITH A METAL PHOSPHORUS COMPOUND; APPLYING A RESIST; REMOVING THE UNPROTECTED METAL PHOSPHORUS COMPOUND; DISSOLVING THE RESIST; AND SUBJECTING THE SUBSTRATE TO ELECTROLESS OR ELECTROLYTIC TREATMENT.

公开(公告)号：US3588757A

公开(公告)日：1971-06-28

申请号：US3588757D

申请日：1968-10-10

Applicant: SIEMENS AG

Inventor： ANDRASCEK ERNST ,  ROSSHAUPTER ERICH

IPC: H01P3/08 ,  H01P3/13 ,  H05K1/02 ,  H05K1/05 ,  H05K1/14 ,  H05K3/42 ,  H05K3/44 ,  H03H7/10 ,  H01P3/00

CPC classification number: H01P3/081 ,  H01P3/13 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/144 ,  H05K3/42 ,  H05K3/427 ,  H05K3/44 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/037 ,  H05K2201/09554 ,  H05K2201/1006

Abstract: A MICROWAVE CIRCUIT EMPLOYING MULTIPLATE TECHNIQUE IN WHICH TWO PLATES OF DIELECTRIC MATERIAL EACH CARRY ON ONE SIDE THEREOF A CONTINUOUS METAL LAYER AND ON THE OTHER SIDE CONDUCTOR TRACKS FORMING MICROWAVE CIRCUIT ELEMENTS, WITH SUCH PLATES BEING SUPERIMPOSED WITH THEIR SIDES CARRYING SUCH CONDUCTOR TRACKS IN OPPOSED RELATION, AND COMPRESSION FORCES APPLIED THERETO, CHARACTERIZED BY THE DIELECTRIC BEING IN THE FORM OF A RELATIVELY THINC COATING ON ONE SIDE OF RESPECTIVE RELATIVELY THICK METAL PLATES AND THE CONDUCTOR TRACKS BEING DISPOSED THE OUTER FACE OF THE RESPECTIVE DIELECTRIC COATINGS, THE RESPECTIVE PLATES AND ASSOCIATED DIELECTRIC COATINGS HAVING PERFORATIONS EXTENDING THERETHROUGH, THE WALLS OF THE APERTURES BEING COATED WITH A METALLIT LAYER EXTENDING FROM SELECTED CONDUCTOR TRACKS TO THE ASSOCIATED METAL PLATE TO CONDUCTIVELY CONNECT THE SAME.

公开(公告)号：US3522085A

公开(公告)日：1970-07-28

申请号：US3522085D

申请日：1969-07-09

Applicant: SANYO ELECTRIC CO

Inventor： WATANABE KAZUO

IPC: H01C7/00 ,  H05K1/16 ,  H05K3/06 ,  H05K3/18 ,  H05K3/38 ,  H05K3/30

CPC classification number: H05K1/167 ,  H01C7/00 ,  H05K3/06 ,  H05K3/184 ,  H05K3/381 ,  H05K2201/0344 ,  H05K2203/1152 ,  H05K2203/1453 ,  Y10S428/936 ,  Y10T29/49155 ,  Y10T428/12396 ,  Y10T428/12431 ,  Y10T428/12472 ,  Y10T428/12535 ,  Y10T428/1291 ,  Y10T428/12944

公开(公告)号：US2728693A

公开(公告)日：1955-12-27

申请号：US37600153

申请日：1953-08-24

Applicant: MOTOROLA INC

Inventor： CADO ERWIN E

IPC: H05K3/04 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K3/048 ,  H05K3/04 ,  H05K3/108 ,  H05K3/184 ,  H05K2201/0344 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/0743 ,  Y10T29/49155

公开(公告)号：US09980371B2

公开(公告)日：2018-05-22

申请号：US15044380

申请日：2016-02-16

Applicant: IBIDEN CO., LTD.

Inventor： Takayuki Katsuno ,  Yuki Ito ,  Takeshi Furusawa ,  Takema Adachi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/24 ,  H05K3/02 ,  H05K3/18

CPC classification number: H05K1/0271 ,  H05K3/007 ,  H05K3/025 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

公开(公告)号：US20180124925A1

公开(公告)日：2018-05-03

申请号：US15572506

申请日：2016-06-01

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Kayo HASHIZUME ,  Yoshio OKA ,  Takashi KASUGA ,  Jinjoo PARK ,  Hiroshi UEDA

IPC: H05K3/38 ,  B32B15/20 ,  B32B15/088 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K3/388 ,  B32B15/08 ,  B32B15/088 ,  B32B15/20 ,  B32B2307/202 ,  B32B2457/08 ,  H05K1/09 ,  H05K1/097 ,  H05K3/022 ,  H05K3/381 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2203/0766 ,  H05K2203/0793 ,  H05K2203/095

Abstract: According to an embodiment of the present invention, a substrate for a printed circuit board, the substrate including a resin film and a metal layer deposited on at least one surface of the resin film, includes a modified layer on the surface of the resin film on which the metal layer is deposited, the modified layer having a composition different from another portion, in which the modified layer contains a metal, a metal ion, or a metal compound different from a main metal of the metal layer. The content of a metal element of the metal, the metal ion, or the metal compound on a surface of the modified layer is preferably 0.2 atomic % or more and 10 atomic % or less.

公开(公告)号：US20170013710A1

公开(公告)日：2017-01-12

申请号：US14849614

申请日：2015-09-10

Applicant: Subtron Technology Co., Ltd.

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Mei-Chin Chang ,  Ching-Ta Chen

IPC: H05K1/09 ,  H05K3/18 ,  H05K1/11

CPC classification number: H05K1/09 ,  H05K1/111 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/072

Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。

公开(公告)号：US09408307B2

公开(公告)日：2016-08-02

申请号：US14382801

申请日：2013-03-05

Applicant: KYOCERA Corporation

Inventor： Mahiro Tsujino ,  Eiichi Katayama ,  Emi Mukai ,  Atsushi Ogasawara

IPC: H05K5/00 ,  H05K1/18 ,  H01L23/057 ,  H05K1/16

CPC classification number: H05K1/181 ,  H01L23/057 ,  H01L2924/0002 ,  H05K1/162 ,  H05K1/167 ,  H05K1/184 ,  H05K1/189 ,  H05K2201/0344 ,  H05K2201/10075 ,  H05K2201/10083 ,  H05K2201/10143 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/10196 ,  H01L2924/00

Abstract: A device housing package includes a substrate in a form of a rectangle, having a mounting region of a device at an upper surface thereof; a frame body disposed on the substrate so as to extend along an outer periphery of the mounting region, the frame body having a cutout formed at a part thereof; and an input-output terminal disposed in the cutout. The input-output terminal includes a first insulating layer, a second insulating layer overlaid on the first insulating layer, and a third insulating layer overlaid on the second insulating layer. First terminals set at a predetermined potential are disposed on an upper surface of the first insulating layer. Second terminals set at a predetermined potential are disposed on a lower surface of the first insulating layer. Third terminals through which AC signals flow are disposed on an upper surface of the second insulating layer.

Abstract translation: 一种器件外壳封装，包括矩形形式的衬底，在其上表面具有器件的安装区域; 框架体，其设置在所述基板上，以沿着所述安装区域的外周延伸，所述框体具有在其一部分处形成的切口; 以及设置在所述切口中的输入输出端子。 输入输出端子包括第一绝缘层，覆盖在第一绝缘层上的第二绝缘层和覆盖在第二绝缘层上的第三绝缘层。 设置在预定电位的第一端子设置在第一绝缘层的上表面上。 设置在预定电位的第二端子设置在第一绝缘层的下表面上。 AC信号流过的第三端子设置在第二绝缘层的上表面上。