公开(公告)号：US20100186231A1

公开(公告)日：2010-07-29

申请号：US12654850

申请日：2010-01-06

Applicant: Jurgen Schulz-Harder ,  Peter Haberl

Inventor： Jurgen Schulz-Harder ,  Peter Haberl

IPC: H01B19/00

CPC classification number: H05K3/4667 ,  H01L23/3735 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/162 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/28 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09972 ,  H05K2203/1476 ,  Y10T29/49227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

Abstract translation: 本发明涉及一种用于电路或模块的金属陶瓷衬底，所述衬底包括陶瓷层，该陶瓷层设置有以平面方式施加到所述陶瓷层表面的至少一种第一类金属层。 由含玻璃的材料构成的绝缘层被施加到第一类型的金属层的表面的至少一个部分区域，与陶瓷层相对的所述表面和第二类型的金属层施加到 绝缘层，绝缘层和第二类型的金属层分别比陶瓷层和第一类型的金属层薄。

公开(公告)号：US07750461B2

公开(公告)日：2010-07-06

申请号：US10515633

申请日：2003-04-11

Applicant: Jürgen Schulz-Harder ,  Peter Haberl

Inventor： Jürgen Schulz-Harder ,  Peter Haberl

IPC: H01L23/12 ,  H01L23/053

CPC classification number: H05K3/4667 ,  H01L23/3735 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/162 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/28 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09972 ,  H05K2203/1476 ,  Y10T29/49227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

Abstract translation: 本发明涉及一种用于电路或模块的金属陶瓷衬底，所述衬底包括陶瓷层，该陶瓷层设置有以平面方式施加到所述陶瓷层表面的至少一种第一类金属层。 由含玻璃的材料构成的绝缘层被施加到第一类型的金属层的表面的至少一个部分区域，与陶瓷层相对的所述表面和第二类型的金属层施加到 绝缘层，绝缘层和第二类型的金属层分别比陶瓷层和第一类型的金属层薄。

公开(公告)号：US20100163287A1

公开(公告)日：2010-07-01

申请号：US12574350

申请日：2009-10-06

Applicant: Chih-Cheng LEE

Inventor： Chih-Cheng LEE

IPC: H05K1/09 ,  H05K1/00 ,  B44C1/22

CPC classification number: H05K3/4007 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/112 ,  H05K3/243 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract translation: 提供了基板结构。 基板结构包括基板，第一绝缘层，导电部件，第二绝缘层，种子层和导电层。 衬底具有分别位于衬底的两个相对表面上的第一电路图案层和第二电路图案层。 形成在第一电路图案层上的第一绝缘层具有第一绝缘孔，其暴露第一绝缘层的外表面中的第一开口。 形成在与芯片电连接的第一绝缘孔上的导电部分被第一开口的边缘包围。 形成在第二电路图案层上的第二绝缘层具有形成种子层的第二绝缘孔。 导电层形成在种子层上，用于与电路板电连接。

公开(公告)号：US07732935B2

公开(公告)日：2010-06-08

申请号：US11408123

申请日：2006-04-20

Applicant: Eiji Moriyama

Inventor： Eiji Moriyama

IPC: H01L23/48

CPC classification number: H05K3/243 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49894 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48799 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81024 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0268 ,  H05K3/282 ,  H05K3/328 ,  H05K3/341 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/10674 ,  H05K2203/162 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/43 ,  H01L2924/01006

Abstract: A wiring board includes a substrate made of an insulation material and wired by a conductive material. A plurality of electrodes is formed on a surface of the substrate. A non-Au electrode not having an Au surface layer and an Au electrode having the Au surface layer are formed as the electrodes.

Abstract translation: 布线板包括由绝缘材料制成并由导电材料布线的基板。 在基板的表面上形成多个电极。 形成不具有Au表面层的非Au电极和具有Au表面层的Au电极作为电极。

公开(公告)号：US20100032202A1

公开(公告)日：2010-02-11

申请号：US11658877

申请日：2006-07-07

Applicant: Hideki Higashitani

Inventor： Hideki Higashitani

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4069 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/384 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/1461 ,  Y10T29/49124

Abstract: A wiring substrate of the invention comprises electrical insulation substrate (1), through-hole (3) formed in the electrical insulation substrate, electrically conductive paste (4) filled inside the through-hole, and wiring traces (11) formed on one or both surfaces of the electrical insulation substrate and electrically connected with the electrically conductive paste, wherein interfaces of the wiring traces in contact with the electrically conductive paste have at least one of an asperate surface and a smooth surface, and a plurality of granular bumps (14) formed further thereon.

Abstract translation: 本发明的布线基板包括电绝缘基板（1），形成在电绝缘基板中的通孔（3），填充在通孔内部的导电浆料（4）和形成在一个或多个 电绝缘基板的两个表面并与导电浆料电连接，其中与导电浆料接触的布线迹线的界面具有平坦表面和光滑表面中的至少一个，以及多个颗粒凸块（14） ）。

公开(公告)号：US07638872B2

公开(公告)日：2009-12-29

申请号：US11595082

申请日：2006-11-09

Applicant: Christian Goebl ,  Karlheinz Augustin

Inventor： Christian Goebl ,  Karlheinz Augustin

IPC: H01L23/48

CPC classification number: H05K3/4007 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L25/072 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/19107 ,  H01L2924/20757 ,  H05K1/0265 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/4046 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2203/049 ,  H01L2924/00

Abstract: A power semiconductor module is presented. The power semiconductor module has a substrate, a composite film, and a power semiconductor component between the substrate and the composite film. The composite film has a thin circuit-structured logic metal layer and a thick circuit-structured power metal layer and between them a thin electrically insulating plastic film. The composite film includes contact nubs, which provide bonding to the power semiconductor component. Feedthrough holes are provided between the logic metal layer and the power metal layer. The plastic film in the region of the respective through-plated hole includes a recess in a region that is free of the logic metal layer. A segment of a flexible thin wire extends through the free region of the logic metal layer and through the recess in the plastic film and is bonded to the logic metal layer and the power metal layer by means of bonding sites.

Abstract translation: 介绍了功率半导体模块。 功率半导体模块在基板和复合膜之间具有基板，复合膜和功率半导体部件。 复合膜具有薄的电路结构的逻辑金属层和厚电路结构的功率金属层，并且在它们之间是薄的电绝缘塑料膜。 复合膜包括提供与功率半导体部件的接合的接触凸块。 在逻辑金属层和功率金属层之间提供穿通孔。 在相应的通孔的区域中的塑料膜包括在没有逻辑金属层的区域中的凹部。 柔性细线的一段延伸穿过逻辑金属层的自由区域并穿过塑料膜中的凹槽，并通过结合位点结合到逻辑金属层和功率金属层。

公开(公告)号：US20090288872A1

公开(公告)日：2009-11-26

申请号：US12219078

申请日：2008-07-15

Applicant: Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

Inventor： Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

IPC: H05K1/02 ,  H05K3/36

CPC classification number: H05K3/462 ,  H05K1/0265 ,  H05K1/0366 ,  H05K3/025 ,  H05K3/108 ,  H05K3/4623 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: Disclosed herein is a printed circuit board including an outmost fine circuit pattern. In the board, an end of a via, which has the minimum diameter, is connected to the outmost circuit layer of a substrate. The end surface, having the minimum diameter, is positioned at the outmost layer, so that the outmost circuit layer of the substrate, which needs to have a relatively high density in order to mount chips, compared to other circuit layers, can be more finely formed.

Abstract translation: 这里公开了包括最外部的精细电路图案的印刷电路板。 在板中，具有最小直径的通孔的端部连接到基板的最外层电路层。 具有最小直径的端面位于最外层，使得与其它电路层相比，为了安装芯片而需要具有相对较高密度的衬底的最外层电路层可以更细 形成。

公开(公告)号：US20090266588A1

公开(公告)日：2009-10-29

申请号：US12488299

申请日：2009-06-19

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/03 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board has a core substrate, an interlayer insulation layer formed over the core substrate, conductive layers formed over the core substrate, and a via hole for providing electrical connection between the conductive layers. The conductive layers include a conductive layer formed on the core substrate, and the conductive layer formed on the core substrate has a side face in a form of rounded taper tapering toward the core substrate.

Abstract translation: 多层印刷电路板具有芯基板，在芯基板上形成的层间绝缘层，形成在芯基板上的导电层，以及用于在导电层之间提供电连接的通孔。 导电层包括形成在芯基板上的导电层，并且形成在芯基板上的导电层具有朝向芯基板渐缩的圆锥形的侧面。

公开(公告)号：US20090211787A1

公开(公告)日：2009-08-27

申请号：US12369029

申请日：2009-02-11

Applicant: Katsutoshi KAMEI ,  Voonyee HO

Inventor： Katsutoshi KAMEI ,  Voonyee HO

IPC: H05K1/00

CPC classification number: H05K1/0248 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0245 ,  H05K1/056 ,  H05K2201/0352 ,  H05K2201/09672 ,  H05K2201/09727

Abstract: A first insulating layer is formed on a suspension body, and a write wiring trace and a read wiring trace are formed on the first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover the wiring traces. A write wiring trace and a read wiring trace are formed on the second insulating layer. A third insulating layer is formed on the second insulating layer so as to cover the wiring traces. The width of the wiring trace is larger than the width of the wiring trace, and the width of the wiring trace is larger than the width of the wiring trace.

Abstract translation: 在悬架体上形成第一绝缘层，在第一绝缘层上形成写入布线迹线和读取布线迹线。 在第一绝缘层上形成第二绝缘层以覆盖布线迹线。 写入布线迹线和读取布线迹线形成在第二绝缘层上。 在第二绝缘层上形成第三绝缘层以覆盖布线迹线。 布线的宽度大于布线的宽度，布线的宽度大于布线的宽度。

公开(公告)号：US20090205202A1

公开(公告)日：2009-08-20

申请号：US12351954

申请日：2009-01-12

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H05K3/30

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K1/036 ,  H05K1/188 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层，第二绝缘层和导电膜的基底基板的方法制造印刷电路板。 在基于对准标记确定的位置处将电子部件放置在第一绝缘层上。 在将电子部件封闭在第二绝缘层的开口内之后，在基于对准标记确定的位置处形成暴露电子部件的端子的通孔，该位置用于确定电子部件的位置。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。