公开(公告)号：US20140000951A1

公开(公告)日：2014-01-02

申请号：US13997420

申请日：2011-12-23

Applicant: Sung Wuk Ryu ,  Seong Bo Shim ,  Seung Yul Shin

Inventor： Sung Wuk Ryu ,  Seong Bo Shim ,  Seung Yul Shin

IPC: H05K1/02 ,  H05K3/40

CPC classification number: H05K1/02 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/40 ,  H05K3/4007 ,  H05K2201/0367

Abstract: A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.

Abstract translation: 根据本发明的实施例的印刷电路板包括绝缘层，形成在绝缘层上并通过阻焊剂的开口部分暴露的焊盘，通过从焊料的顶部填充阻焊剂的开口部而形成的凸块 该焊盘的宽度比阻焊剂的开口宽。

公开(公告)号：US08586409B2

公开(公告)日：2013-11-19

申请号：US11662940

申请日：2005-09-29

Applicant: Cécile Davoine ,  Manuel Fendler

Inventor： Cécile Davoine ,  Manuel Fendler

IPC: H01L21/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/114 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83894 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10977 ,  H05K2203/0278 ,  Y10T29/49126 ,  H01L2224/13099 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of electrical connection between a series of hard conductive points and corresponding pads arranged on a one face of a first component, and a series of buried ductile conductive bumps and corresponding pads arranged on one face of a second component. The method comprises forming said series of hard conductive points on said face of the first component; forming said series of buried ductile conducting bumps on said face of the second component; inserting said series of hard conductive points in said series of buried ductile conducting bumps at an ambient temperature; and directly sealing the first and second components together.

Abstract translation: 一系列硬导电点和布置在第一部件的一个面上的对应焊盘之间的电连接的方法，以及布置在第二部件的一个面上的一系列埋地延性导电凸块和相应的焊盘。 该方法包括在第一部件的所述面上形成所述一系列硬导电点; 在所述第二部件的所述面上形成所述一系列埋入的延性传导凸块; 在环境温度下将所述一系列硬导电点插入所述一系列埋地延性传导凸块中; 并将第一和第二部件直接密封在一起。

公开(公告)号：US20130286619A1

公开(公告)日：2013-10-31

申请号：US13929291

申请日：2013-06-27

Applicant: Tessera, Inc.

Inventor： Jinsu Kwon ,  Kimitaka Endo ,  Sean P. Moran

IPC: H05K1/11

CPC classification number: H05K1/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0384 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00

Abstract: An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed.

Abstract translation: 提供互连元件用于与具有微电子器件或其上的布线中的至少一个的另一元件的导电互连。 互连元件包括具有主表面的电介质元件。 包括多个暴露的金属柱的电镀金属层可以向外突出超过介电元件的主表面。 一些金属柱可以通过电介质元件彼此电绝缘。 互连元件通常包括与金属柱导电连通的多个端子。 端子可以通过电介质元件连接到金属柱。 可以通过将金属镀在芯棒的暴露的共平面表面和心轴中的开口的内表面上来定义柱，然后可以去除心轴。

公开(公告)号：US20130264711A1

公开(公告)日：2013-10-10

申请号：US13897480

申请日：2013-05-20

Applicant: The Boeing Company

Inventor： Keith Daniel Humfeld

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H05K3/222 ,  B82Y30/00 ,  H01L21/76838 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0367 ,  H05K2201/10363 ,  H01L2924/00

Abstract: A fabricated substrate has at least one plurality of posts. The plurality is fabricated such that the two posts are located at a predetermined distance from one another. The substrate is exposed to a fluid matrix containing functionalized carbon nanotubes. The functionalized carbon nanotubes preferentially adhere to the plurality of posts rather than the remainder of the substrate. A connection between posts of the at least one plurality of posts is induced by adhering one end of the functionalized nanotube to one post and a second end of the functionalized carbon nanotube to a second post.

Abstract translation: 制造的基板具有至少多个柱。 多个制造成使得两个柱彼此相隔预定距离。 将基底暴露于含有官能化碳纳米管的流体基质。 功能化的碳纳米管优先粘附到多个柱而不是衬底的其余部分。 通过将功能化纳米管的一端粘附到官能化碳纳米管的一个柱和第二端到第二柱来诱导至少一个多个柱的柱之间的连接。

公开(公告)号：US20130243941A1

公开(公告)日：2013-09-19

申请号：US13889064

申请日：2013-05-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seok Kyu LEE ,  Soon Oh Jung ,  Jong Kuk Hong ,  Soon Jin Cho

IPC: H05K3/00

CPC classification number: H05K3/00 ,  H05K1/113 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/426 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/054 ,  H05K2203/1572

Abstract: A method of manufacturing a coreless substrate having filled via pads, including: forming a first insulating layer on one side of a carrier forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; removing the carrier, and forming via-holes in the first and second insulating layers; and conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.

Abstract translation: 一种制造具有填充通孔焊盘的无芯基板的方法，包括：在载体的一侧上形成第一绝缘层，形成包含积聚绝缘层的堆积层和具有堆积层的积聚电路层 通过所述第一绝缘层，并且在所述积层上形成第二绝缘层; 移除所述载体，以及在所述第一和第二绝缘层中形成通孔; 并且在第一和第二绝缘层的通孔中进行填充电镀处理，从而在其中形成第一和第二填充的通孔焊盘。

公开(公告)号：US20130234328A1

公开(公告)日：2013-09-12

申请号：US13873509

申请日：2013-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Teck Kheng Lee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1012 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81138 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/20105 ,  H01L2924/20106 ,  H05K3/06 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0315 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012

Abstract: A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

公开(公告)号：US08487432B2

公开(公告)日：2013-07-16

申请号：US12907430

申请日：2010-10-19

Applicant: Glenn A. Rinne ,  J. Daniel Mis

Inventor： Glenn A. Rinne ,  J. Daniel Mis

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2924/00014 ,  H01L2924/013

Abstract: An electronic device may include a substrate, a seed layer on the substrate, a barrier layer on the seed layer opposite the substrate, and an oxidation barrier on the barrier layer opposite the seed layer. The barrier layer and the seed layer comprise different materials, and the oxidation barrier and the barrier layer may comprise different materials. The seed layer may be undercut relative to the barrier layer and/or relative to the oxidation barrier so that the barrier layer and/or the oxidation barrier define a lip extending beyond the seed layer in a direction parallel with respect to a surface of the substrate. Related methods are also discussed.

Abstract translation: 电子器件可以包括衬底，衬底上的种子层，与衬底相对的种子层上的阻挡层以及与种子层相对的阻挡层上的氧化屏障。 阻挡层和种子层包含不同的材料，氧化屏障和阻挡层可以包括不同的材料。 种子层可以相对于阻挡层和/或相对于氧化屏障而被切削，使得阻挡层和/或氧化屏障在相对于衬底的表面平行的方向上限定延伸超过种子层的唇缘 。 还讨论了相关方法。

公开(公告)号：US08479388B2

公开(公告)日：2013-07-09

申请号：US12207713

申请日：2008-09-10

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01K3/10

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US08464423B2

公开(公告)日：2013-06-18

申请号：US13373387

申请日：2011-11-14

Applicant: Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC: H01R9/00 ,  H01R43/16 ,  H01R43/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/10

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

Abstract translation: 一种制造具有金属凸块的印刷电路板的方法，包括：在第一载体上形成用于形成金属凸块的凹部，在第一载体上形成第一阻挡层，并在第一阻挡层上形成上电路层 所述上电路层包括充电在所述凹部中的金属凸块和电路图案; 在第二载体上形成第二阻挡层，并在第二阻挡层上形成下电路层; 制备绝缘层，并将上下电路层转移到绝缘层; 移除第一和第二载体; 以及去除所述第一和第二阻挡层。

公开(公告)号：US08440915B2

公开(公告)日：2013-05-14

申请号：US12915852

申请日：2010-10-29

Applicant: Masayuki Nagamatsu ,  Kiyoshi Shibata ,  Takanori Hayashi

Inventor： Masayuki Nagamatsu ,  Kiyoshi Shibata ,  Takanori Hayashi

IPC: H05K1/11

CPC classification number: H05K3/3452 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/0367 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/0588 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided on a first device mounting board constituting a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. A first insulating layer having an opening is provided on one main surface of an insulating resin layer which is a substrate, and an electrode portion, whose top portion protrudes above the top surface of the first insulating layer, is formed in the opening. A second insulating layer is provided on top of the first insulating layer in the periphery of the top portion of the first electrode portion; the second insulting layer is located slightly apart from the top portion of the first electrode portion. The first electrode portion is shaped such that the top portion is formed by a curved surface or formed by a curved surface and a plane surface smoothly connected to the curved surface.

Abstract translation: 半导体器件具有PoP结构，使得设置在构成第一半导体模块的第一器件安装板上的第一电极部分和设置在第二半导体器件中的第二电极部分通过焊球接合在一起。 具有开口的第一绝缘层设置在作为基板的绝缘树脂层的一个主表面上，并且其顶部突出于第一绝缘层的顶表面上方的电极部分形成在开口中。 在第一电极部分的顶部周边的第一绝缘层的顶部上设置第二绝缘层; 第二绝缘层位于与第一电极部分的顶部稍微分开的位置。 第一电极部分被成形为使得顶部由弯曲表面形成或由曲面形成并且平坦表面平滑地连接到弯曲表面。