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    Multiconductor interconnect
    52.
    发明授权
    Multiconductor interconnect 有权
    多导体互连

    公开(公告)号：US06471415B1

    公开(公告)日：2002-10-29

    申请号：US09618207

    申请日：2000-07-18

    Applicant: Paul W. Poorman

    Inventor： Paul W. Poorman

    IPC: G02B638

    CPC classification number: H01R12/613 ,  G11B5/00821 ,  G11B5/10 ,  G11B5/3103 ,  G11B5/4893 ,  H01R31/06 ,  H05K1/117 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/0919 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2203/049

    Abstract: A space saving interconnect having a plurality of conductors. To decrease the width of a selected portion of the interconnect, the conductors are split between two or more layers. One group the conductors extend along a portion of a first layer jumping to and continuing along a second layer. The remaining conductors extend only along the first layer. Consequently, the width of the interconnect where the conductors are split between the layers can be substantially reduced. In one exemplary embodiment, the first layer is characterized by a first section having only first conductors and a second section having both the first second conductors. The first conductors in the first section of the first layer span a first width and the first and second conductors in the second section of the first layer span a second width greater than the first width. The second layer includes third conductors extending between first and second sections of the second layer. The third conductors in the first section of the second layer span a third width, and the third conductors in the second section of the second layer span a fourth width.

    Abstract translation: 具有多个导体的节省空间的互连。 为了减小互连选定部分的宽度，导体在两层或更多层之间分开。 一组导体沿第一层的一部分延伸，跳到第二层并继续沿第二层延伸。 剩余的导体仅沿着第一层延伸。 因此，可以显着地减少导体在层之间分裂的互连的宽度。 在一个示例性实施例中，第一层的特征在于仅具有第一导体的第一部分和具有两个第一第二导体的第二部分。 第一层的第一部分中的第一导体跨越第一宽度，并且第一层的第二部分中的第一和第二导体跨越大于第一宽度的第二宽度。 第二层包括在第二层的第一和第二部分之间延伸的第三导体。 第二层的第一部分中的第三导体跨越第三宽度，并且第二层的第二部分中的第三导体跨越第四宽度。

    Multi in-line memory module and matching electronic component socket
    53.
    发明授权
    Multi in-line memory module and matching electronic component socket 有权
    多行内存模块和匹配电子元件插座

    公开(公告)号：US06421250B1

    公开(公告)日：2002-07-16

    申请号：US09405514

    申请日：1999-09-23

    Applicant: Jong-ryeul Kim ,  Jung-joon Lee ,  Bok-moon Kang

    Inventor： Jong-ryeul Kim ,  Jung-joon Lee ,  Bok-moon Kang

    IPC: H05K111

    CPC classification number: H05K1/144 ,  G11C5/04 ,  H01R12/721 ,  H05K1/117 ,  H05K2201/09163 ,  H05K2201/0919

    Abstract: A multi in-line module and an electronic component socket for the multi in-line module are provided. One embodiment of a multi in-line memory module includes a printed circuit board having at least two protrusions formed along one edge of the printed circuit board. Each of the protrusions has first and second surfaces for blocks of contact pins. Accordingly, the module can include three or more pin blocks on separate surfaces of the protrusions. The module provides a large number of pins without being significantly larger than a conventional SIMM or DIMM. Alternatively, physical and electrical attachment of multiple circuit boards provides three or more independent pin blocks on the various surfaces of the printed circuit boards. A socket for a module includes dielectric protrusions with two or more gaps between the protrusions and contact pins on side surfaces of the protrusions that are in the gaps. Inserting the protrusions of a multi in-line module into the gaps between the protrusions of the socket creates an electrical connection between contact pins on the module and contact pins of the socket.

    Abstract translation: 提供了一种用于多直列模块的多直列模块和电子组件插座。 多列嵌入式存储器模块的一个实施例包括具有沿着印刷电路板的一个边缘形成的至少两个突起的印刷电路板。 每个突起具有用于接触销块的第一和第二表面。 因此，模块可以在突起的分开的表面上包括三个或更多个销块。 该模块提供大量引脚，而不会显着大于常规SIMM或DIMM。 或者，多个电路板的物理和电连接在印刷电路板的各个表面上提供三个或更多个独立的引脚块。 用于模块的插座包括在突起之间具有两个或更多间隙的电介质突起和位于间隙中的突起的侧表面上的接触销。 将多个在线模块的突起插入到插座的突起之间的间隙中，在模块上的接触销和插座的接触销之间形成电连接。

    System and method for metalization of deep vias
    54.
    发明申请
    System and method for metalization of deep vias 审中-公开
    深孔金属化的系统和方法

    公开(公告)号：US20020066179A1

    公开(公告)日：2002-06-06

    申请号：US09727650

    申请日：2000-12-01

    Inventor： Hendley W. Hall ,  Wayne K. Finn

    IPC: H05K003/10 ,  B05C013/02

    CPC classification number: H05K3/4069 ,  H05K3/0035 ,  H05K3/0047 ,  H05K2201/0919 ,  H05K2201/09518 ,  H05K2203/0126 ,  H05K2203/0207 ,  H05K2203/163 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: In a method of injecting an electrically conductive epoxy into blind vias during drilling or shortly thereafter in order to avoid oxidation of the copper or other metal of the imbedded layer, a machine tool is provided with at least one controllable spindle and at least one injection device. Alternatively, two machine tools, one with at least one controllable spindle and one with at least one injection device, may be provided. A printed circuit board mounted on the machine tool table for drilling is registered in the usual way for the particular machine tool. The machine tool part program then drills a particular pattern for the circuit board for mounting of circuit board components. All of the blind vias as well as through hole vias are drilled at one time by the machine tool by the tools mounted in the spindle or by laser drilling systems, but may also be drilled and filled in any sequence. The drilling operation is followed by the epoxy injecting operation in which a controlled operating device, comprising a reservoir, a pumping mechanism, a hollow needle through which the conductive epoxy flows to the bottom of the hole, a control mechanism, and sensors detect various mechanism operations and when hole fill is completed.

    Abstract translation: 在钻孔期间或之后不久将导电环氧树脂注入盲孔的方法中，为了避免铜或嵌入层的其它金属的氧化，机床上设置有至少一个可控心轴和至少一个注射装置 。 或者，可以提供两个机床，一个具有至少一个可控心轴，一个具有至少一个注射装置。 以特定机床的通常方式登记安装在机床台上用于钻孔的印刷电路板。 然后，机床零件程序为用于安装电路板部件的电路板钻出特定图案。 所有的盲孔和通孔通过机床一次通过安装在主轴上的工具或激光钻孔系统一次钻孔，但也可以以任何顺序钻孔和填充。 钻孔操作之后是环氧注射操作，其中包括储存器，泵送机构，导电环氧树脂流过孔的底部的空心针，控制机构和传感器的受控操作装置检测各种机构 操作和填充孔时。

    Capacitor laminate for use in printed circuit board and as an interconnector
    56.
    发明授权
    Capacitor laminate for use in printed circuit board and as an interconnector 有权
    电容层压板用于印刷电路板和互连器

    公开(公告)号：US06370012B1

    公开(公告)日：2002-04-09

    申请号：US09652596

    申请日：2000-08-30

    Applicant: Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

    Inventor： Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

    IPC: H01G4228

    CPC classification number: H05K1/053 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/162 ,  H05K3/403 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0919 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/417 ,  H01L2924/00

    Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

    Abstract translation: 能够形成较大的电路板或类似结构的内部部分以提供电容的并联电容器结构。 或者，电容器可以用作互连器以互连两个不同的电子部件（例如，芯片载体，电路板，甚至半导体芯片），同时仍然为一个或多个所述部件提供期望的电容水平。 电容器包括至少一个内部导电层，在内部导体的相对侧上添加两个附加的导体层，以及无机介电材料（优选地，在第二导体层的外表面上的氧化物层或适用于诸如钛酸钡的适当介电材料 第二导体层）。 此外，电容器包括无机介电材料顶部的外部导体层，从而在内部和附加的导电层和外部导体之间形成并联的电容器。

    Multi-chip module having an integral capacitor element
    58.
    发明授权
    Multi-chip module having an integral capacitor element 失效
    具有整体电容器元件的多芯片模块

    公开(公告)号：US6061228A

    公开(公告)日：2000-05-09

    申请号：US67606

    申请日：1998-04-28

    Applicant: Edward G. Palmer ,  Charles M. Newton

    Inventor： Edward G. Palmer ,  Charles M. Newton

    IPC: H01L23/538 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H01G4/228 ,  H01G4/06

    CPC classification number: H01L23/5384 ,  H05K1/162 ,  H01L2224/48091 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0187 ,  H05K2201/0919 ,  H05K3/0052 ,  H05K3/4053 ,  Y10T29/435

    Abstract: A multi-chip module has an integral capacitor element embedded within the substrate and includes a plurality of substrate layers forming a multi-chip module substrate. The substrate has a cut edge and forms at the cut edge a bondable edge. A via is formed in the substrate, and a dielectric capacitive material fills the via for a plurality of substrate layers and defines a multilayer capacitor. The multilayer capacitor and via are positioned at the bondable edge and connects to the bondable edge. In one aspect, the via having the dielectric capacitive material is positioned at the cut edge, and includes a conductive material filling at least a portion of the cut via to form the bondable edge. The dielectric capacitive material and bondable edge form a junction surface. A signal trace can be formed on a substrate layer and connected to the capacitor to form a DC blocking capacitor structure. A ground line can be formed on one substrate layer and engage the capacitive material. A signal trace can be formed on one of the substrate layers and engage the bondable edge to define a decoupling capacitor structure.

    Abstract translation: 多芯片模块具有嵌入在基板内的积分电容器元件，并且包括形成多芯片模块基板的多个基板层。 基板具有切割边缘并且在切割边缘处形成可结合边缘。 在衬底中形成通孔，并且介电电容材料填充用于多个衬底层的通孔，并且限定多层电容器。 多层电容器和通孔位于可结合边缘并连接到可结合边缘。 在一个方面，具有介电电容材料的通孔位于切割边缘处，并且包括填充切割通孔的至少一部分以形成可结合边缘的导电材料。 电介质电容材料和可结合边缘形成接合面。 信号迹线可以形成在衬底层上并连接到电容器以形成直流隔离电容器结构。 接地线可以形成在一个衬底层上并与电容材料接合。 信号迹线可以形成在一个衬底层上并且与可结合边缘接合以限定去耦电容器结构。

    Method of manufacturing magnetic head suspension having circuit wiring pattern
    60.
    发明授权
    Method of manufacturing magnetic head suspension having circuit wiring pattern 失效
    制造具有电路布线图案的磁头悬挂方法

    公开(公告)号：US5809634A

    公开(公告)日：1998-09-22

    申请号：US848831

    申请日：1997-05-05

    Applicant: Masaichi Inaba

    Inventor： Masaichi Inaba

    IPC: G11B5/60 ,  G11B5/48 ,  G11B21/02 ,  G11B21/21 ,  H05K1/05 ,  H05K3/00 ,  H05K3/28 ,  H05K3/44 ,  G11B5/42

    CPC classification number: G11B5/4853 ,  G11B5/48 ,  H05K3/44 ,  H05K1/056 ,  H05K2201/0919 ,  H05K2203/0554 ,  H05K2203/1476 ,  H05K3/002 ,  H05K3/0032 ,  H05K3/0041 ,  H05K3/28 ,  Y10T29/49027

    Abstract: A method of manufacturing a magnetic head suspension having a circuit wiring pattern member, comprises the steps of: preparing a laminated plate composed of a flat flexible insulating base member (2), a conductive layer (9 or 3) formed on one surface thereof, and an elastic metal layer (8 or 1) formed on the other surface thereof; photo-etching the conductive layer of the laminated plate, to form a metal mask (9) of a desired flexible insulating base member shape; removing the exposed flexible insulating base member (2) to such a thickness that the elastic metal layer (8 or 1) is at least not exposed; photo-etching the formed metal mask (9), to form a desired circuit wiring pattern (3); further etching the flexible insulating base member (2), to remove a part of the flexible insulating base member (2) still remaining on the surface of the elastic metal layer (8 or 1) in the preceding step, by using the formed circuit wiring pattern (3) as a mask; forming a surface protecting layer (4) on the surface of the formed circuit wiring pattern (3) and photo-etching the elastic metal layer (8) and bending the photo-etched elastic metal layer (8) to a desired shape, to form a suspension (1) of a desired shape.

    Abstract translation: 一种制造具有电路布线图案构件的磁头悬架的方法，包括以下步骤：制备由平面柔性绝缘基底构件（2），形成在其一个表面上的导电层（9或3）构成的层压板， 和形成在其另一个表面上的弹性金属层（8或1）; 对层压板的导电层进行光蚀刻，以形成所需柔性绝缘基底构件形状的金属掩模（9）; 将暴露的柔性绝缘基底构件（2）去除至使弹性金属层（8或1）至少不暴露的厚度; 对所形成的金属掩模（9）进行光蚀刻以形成期望的电路布线图案（3）; 进一步蚀刻柔性绝缘基底构件（2），以通过使用所形成的电路布线来去除在前一步骤中仍保留在弹性金属层（8或1）的表面上的柔性绝缘基底构件（2）的一部分 图案（3）作为掩模; 在所形成的电路布线图案（3）的表面上形成表面保护层（4），并且对所述弹性金属层（8）进行光蚀刻并将所述光蚀刻的弹性金属层（8）弯曲成所需的形状，以形成 具有所需形状的悬架（1）。

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