公开(公告)号：US20140353022A1

公开(公告)日：2014-12-04

申请号：US14290193

申请日：2014-05-29

Applicant: IBIDEN CO., LTD.

Inventor： Haruhiko MORITA

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/165 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0225 ,  H05K1/0366 ,  H05K1/116 ,  H05K3/244 ,  H05K3/4602 ,  H05K2201/0191 ,  H05K2201/0293 ,  H05K2201/0347 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/09136 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/09836

Abstract: A wiring board includes a substrate having a laminated-inductor forming portion and including multiple first insulation layers and a second insulation layer formed on a first side of the first insulation layers such that the first insulation layers have the laminated-inductor forming portion, and a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate. The laminated-inductor forming portion of the substrate has multiple inductor patterns formed on the first insulation layers and multiple via conductors connecting the inductor patterns through the first insulation layers, and the inductor patterns include an uppermost inductor pattern formed between the second insulation layer and the first insulation layers such that the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor.

Abstract translation: 布线基板包括具有层叠电感器形成部分并且包括多个第一绝缘层的基板和形成在第一绝缘层的第一侧上的第二绝缘层，使得第一绝缘层具有层叠电感器形成部分，以及 形成在基板的第二绝缘层上并形成以屏蔽从基板的层叠电感器形成部分产生的电磁力的平面导体。 衬底的层叠电感器形成部分具有形成在第一绝缘层上的多个电感器图案和通过第一绝缘层连接电感器图案的多个通孔导体，并且电感器图案包括形成在第二绝缘层和 第一绝缘层，使得最上层的电感器图案与平面导体的距离为100μm以上。

公开(公告)号：US08823174B2

公开(公告)日：2014-09-02

申请号：US14108960

申请日：2013-12-17

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US08633591B2

公开(公告)日：2014-01-21

申请号：US13712224

申请日：2012-12-12

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。

公开(公告)号：US08410376B2

公开(公告)日：2013-04-02

申请号：US12840696

申请日：2010-07-21

Applicant: Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K1/11

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole for a via conductor, a conductive circuit formed on one surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and having a protruding portion protruding from the other surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the protruding portion of the via conductor. The via conductor is connected to the conductive circuit and has a first conductive layer formed on the side wall of the penetrating hole and a plated layer filling the penetrating hole.

Abstract translation: 印刷电路板包括：具有用于通路导体的贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的一个表面上的导电电路;形成在该贯通孔中的通孔导体，并且具有从另一个突出的突出部 层间树脂绝缘层的表面和形成在通孔导体的突出部分的表面上的表面处理涂层。 通孔导体连接到导电电路，并且具有形成在穿透孔的侧壁上的第一导电层和填充穿透孔的镀层。

公开(公告)号：US08338718B2

公开(公告)日：2012-12-25

申请号：US12632112

申请日：2009-12-07

Applicant: Kentaro Kaneko ,  Hidemi Atobe

Inventor： Kentaro Kaneko ,  Hidemi Atobe

IPC: H05K1/11

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09436 ,  H05K2201/09527 ,  Y10T29/49162

Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to each other through vias formed in the insulating layers. In the peripheral region around the chip mounting area of the outermost insulating layer on one of both surfaces of the board, a pad is formed in a bump shape to cover a surface of a portion of the outermost insulating layer, the portion being formed to protrude, and a pad whose surface is exposed from the insulating layer is arranged in the chip mounting area. A chip is flip-chip bonded to the pad of the package, and another package is bonded to the bump shaped pad in a peripheral region around the chip (package-on-package bonding).

Abstract translation: 布线板（封装）具有多个布线层一层叠置的结构，绝缘层分别插入在相应的两个布线层之间，并且布线层通过形成在绝缘层中的通孔彼此连接 。 在板的两个表面之一的最外层绝缘层的芯片安装区域周围的周边区域中，形成凸起形状的焊盘以覆盖最外层绝缘层的一部分的表面，该部分形成为突出 并且其表面从绝缘层露出的焊盘被布置在芯片安装区域中。 将芯片倒装芯片贴合到封装的焊盘上，另一个封装在芯片周围的周边区域（封装在封装的封装上）结合到凸块形焊盘。

公开(公告)号：US20110253439A1

公开(公告)日：2011-10-20

申请号：US12818398

申请日：2010-06-18

Applicant: Tzu-Wei Huang

Inventor： Tzu-Wei Huang

IPC: H05K1/11 ,  H05K1/00 ,  H05K3/46 ,  B32B38/10 ,  B23K31/02

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

Abstract translation: 电路基板的制造方法包括以下步骤。 两个金属层的周边结合形成密封区域。 在两个金属层上形成两个绝缘层。 在两个绝缘层上形成包括上，下导电层的两个。 然后，将两个绝缘层和两个导电层层叠，使得彼此接合的两个金属层嵌入在两个绝缘层之间。 去除两个绝缘层的一部分和两个导电层的一部分以形成暴露两个金属层的多个盲孔。 在盲孔和剩余的两个导电层上形成导电材料。 两个金属层的密封区域被分离以形成两个分开的电路基板。

公开(公告)号：US07736457B2

公开(公告)日：2010-06-15

申请号：US11567344

申请日：2006-12-06

Applicant: Yoshiyuki Iwata

Inventor： Yoshiyuki Iwata

IPC: B29C65/02 ,  B32B37/18 ,  B32B38/10

CPC classification number: B32B38/10 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  H05K2203/1536 ,  Y10T29/49165 ,  Y10T156/1056 ,  Y10T156/1057

Abstract: The present invention intends to provide a novel printed wiring board manufacturing method by which printed wiring boards can be manufactured with efficiency. A method of manufacturing a printed wiring board (FIG. 1B) according to the present invention includes a step for preparing two sets of copper clad laminates (FIG. 2A), a step for bonding the copper clad laminates (FIG. 2B), steps for forming lands on both surfaces of a bonded laminate (FIGS. 2C to 2E), steps for forming respective resin layers on both surfaces of the bonded laminate and forming via hole openings to form respective via holes (FIGS. 2F to 2L), a step for forming a resin layer and forming a via hole opening to form a via hole (FIG. 2M), a step for separating the bonded laminate from each other (FIG. 2N) and steps for forming via hole openings from the bonded surface of the separated laminate to form via holes (FIGS. 2O to 2T). Via holes (33-1, 33-2) formed on the resin layer and a via hole (42) formed on the laminate are opened in the opposite directions.

Abstract translation: 本发明旨在提供一种能够有效地制造印刷电路板的新颖的印刷线路板制造方法。 根据本发明的制造印刷电路板（图1B）的方法包括制备两组铜包覆层压板的步骤（图2A），用于粘合覆铜层压板的步骤（图2B），步骤 用于在接合层压体的两个表面上形成焊盘（图2C至2E），用于在接合层叠体的两个表面上形成各个树脂层并形成通孔开口以形成相应的通孔的步骤（图2F至2L）， 用于形成树脂层并形成通孔开口以形成通孔的步骤（图2M），用于将接合的层压体彼此分离的步骤（图2N）和从接合表面形成通孔开口的步骤 分离的层压体以形成通孔（图20至图2T）。 形成在树脂层上的通孔（33-1,33-2）和形成在层叠体上的通孔（42）沿相反方向打开。

公开(公告)号：US20100083490A1

公开(公告)日：2010-04-08

申请号：US12632948

申请日：2009-12-08

Applicant: KENICHI KAWABATA ,  Takaaki Morita

Inventor： KENICHI KAWABATA ,  Takaaki Morita

IPC: H05K3/30 ,  H05K3/10

CPC classification number: H05K3/4652 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/0058 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0358 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/1105 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49128 ,  Y10T428/24917 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A multilayer circuit board comprises core layers 101 and 102 made of a core material impregnated with resin, resin layers 111 and 112 interposed between the core layers 101 and 102, a wiring pattern 140 embedded in the resin layers 111 and 112. The core layers 101 and 102 have a thickness of 100 μm or smaller, whereby the entire board can significantly be thinned. Furthermore, the less strong resin layers 111 and 112 are interposed between the hard core layers 101 and 102, whereby the entire board has increased strength.

Abstract translation: 多层电路板包括由浸渍有树脂的芯材制成的芯层101和102，插入在芯层101和102之间的树脂层111和112，嵌入在树脂层111和112中的布线图案140.芯层101 102的厚度为100μm以下，从而能够使整个基板变薄。 此外，较不强的树脂层111和112插入在硬芯层101和102之间，由此整个板具有增加的强度。

公开(公告)号：US20090260858A1

公开(公告)日：2009-10-22

申请号：US12492429

申请日：2009-06-26

Applicant: Motoo NAKAI ,  Shigeki Nagase

Inventor： Motoo NAKAI ,  Shigeki Nagase

IPC: H05K1/00

CPC classification number: H05K1/0206 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K3/0061 ,  H05K3/244 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0347 ,  H05K2201/0394 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/0959 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Conducting layers and resin-made insulating layers are alternately laminated to form a laminated circuit portion, and a metal substrate is installed so as to be in contact with an insulating layer, which is the lowermost layer. The conducting layers, the insulating layers, and the metal substrate are thermal compression bonded. In order to connect the uppermost conducting layer on which electronic component is placed with the lowermost insulating layer, a conducting layer is formed on the inner surface by copper plating to install a heat dissipating via into which a resin is filled. A conducting layer, which is the uppermost layer, is subjected to gold plating, with nickel plating undercoated. An electronic component for driving a motor is placed on the uppermost conducting layer, by which the metal substrate can be used as a motor drive circuit substrate for an electric power steering system.

Abstract translation: 交替层叠导电层和树脂制绝缘层，以形成层叠电路部分，并且安装金属基板以与作为最下层的绝缘层接触。 导电层，绝缘层和金属基板被热压接。 为了将放置有电子元件的最上层的导电层与最下层绝缘层连接，通过镀铜在内表面上形成导电层，以安装填充有树脂的散热通孔。 作为最上层的导电层进行镀金，镀镍底涂。 用于驱动电动机的电子部件放置在最上层的导电层上，金属基板可以用作电动助力转向系统的电机驱动电路基板。

公开(公告)号：US07594320B2

公开(公告)日：2009-09-29

申请号：US11260077

申请日：2005-10-27

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H01K3/10 ,  H05K3/10

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。