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    Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards
    51.
    发明授权
    Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards 失效
    相邻的电镀通孔具有交错耦合，用于高速印刷电路板中的串扰降低

    公开(公告)号：US07999192B2

    公开(公告)日：2011-08-16

    申请号：US11717634

    申请日：2007-03-14

    Applicant: Jason Edward Chan ,  Jose Ricardo Paniagua

    Inventor： Jason Edward Chan ,  Jose Ricardo Paniagua

    IPC: H05K1/11

    CPC classification number: H01R12/523 ,  H01R12/58 ,  H01R13/6461 ,  H01R13/6477 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09845 ,  H05K2203/0242

    Abstract: An electrical signal connection, an electrical signaling system, and a method of connecting printed circuit boards. The electrical signal connection having a first conductive via and a second conductive via disposed in a first printed circuit board. A first conductive trace with a first end and a second end has the first end electrically coupled to the first conductive via at a first distance from the top surface of the first printed circuit board. The second end of the first conductive via is electrically coupled to the second printed circuit board. A second conductive trace with a first end and a second end has the first end being electrically coupled to the second conductive via at a second distance from the top surface of the first printed circuit board. The second end being is electrically coupled to the second printed circuit board.

    Abstract translation: 电信号连接，电信号系统和连接印刷电路板的方法。 电信号连接具有设置在第一印刷电路板中的第一导电通孔和第二导电通孔。 具有第一端和第二端的第一导电迹线具有与第一印刷电路板的顶表面第一距离处电耦合到第一导电通孔的第一端。 第一导电通孔的第二端电耦合到第二印刷电路板。 具有第一端和第二端的第二导电迹线具有与第一印刷电路板的顶表面相距第二距离的第二导电通孔的第一端电耦合。 第二端电连接到第二印刷电路板。

    MULTILAYER PRINTED CIRCUIT BOARD
    52.
    发明申请
    MULTILAYER PRINTED CIRCUIT BOARD 有权
    多层印刷电路板

    公开(公告)号：US20110011637A1

    公开(公告)日：2011-01-20

    申请号：US12920426

    申请日：2009-03-24

    Applicant: Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

    Inventor： Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

    IPC: H05K1/11

    CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10545 ,  H05K2201/10689

    Abstract: A multilayer printed circuit board, including: a signal interconnection which transmits and receives an electrical signal between electronic components; a ground interconnection connected to a ground of a circuit; a power interconnection connected to a power layer to supply power to electronic components; at least one ground layer installed in an inner layer; at least one clearance which passes through the ground layer; and a ground via which connects the ground interconnection with the ground layer. The signal interconnection and the ground interconnection or the signal interconnection and the power interconnection are installed in a pair, and a pair of interconnection vias for interlayer connection are inserted through the clearance installed in the ground layer so that one of the pair of interconnection vias is connected to the ground layer by the ground interconnection.

    Abstract translation: 一种多层印刷电路板，包括：在电子部件之间传输和接收电信号的信号互连; 连接到电路的地的接地互连; 连接到功率层以向电子部件供电的电力互连; 至少一个地层安装在内层中; 至少一个通过地层的间隙; 以及将接地互连与接地层连接的接地。 信号互连和接地互连，信号互连和电源互连成对安装，并且用于层间连接的一对互连通孔穿过安装在接地层中的间隙插入，使得一对互连通孔中的一个 通过地面互连连接到地层。

    Non-coplanar high-speed interconnects
    53.
    发明授权
    Non-coplanar high-speed interconnects 有权
    非共面高速互连

    公开(公告)号：US07859367B2

    公开(公告)日：2010-12-28

    申请号：US12248456

    申请日：2008-10-09

    Applicant: Yan Yang Zhao ,  Yuheng Lee ,  Jianying Zhou

    Inventor： Yan Yang Zhao ,  Yuheng Lee ,  Jianying Zhou

    IPC: H03H7/38 ,  H01P1/04

    CPC classification number: H01P5/028 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/10689

    Abstract: In one example embodiment, a high-speed package includes first and second layers and a multi-channel non-coplanar interconnect. The first layer includes first and second sets of coplanar transmission lines. The second layer includes third and fourth sets of coplanar transmission lines. The multi-channel non-coplanar interconnect includes first and second channels. The first channel connects the first set of transmission lines to the third set of transmission lines. The second channel connects the second set of transmission lines to the fourth set of transmission lines.

    Abstract translation: 在一个示例实施例中，高速封装包括第一和第二层以及多通道非共面互连。 第一层包括第一和第二组共面传输线。 第二层包括第三和第四组共面传输线。 多通道非共面互连包括第一和第二通道。 第一通道将第一组传输线连接到第三组传输线。 第二通道将第二组传输线连接到第四组传输线。

    Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise
    55.
    发明授权
    Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise 有权
    包括用于抑制电力和接地平面噪声的结构的基板，系统和装置，以及用于抑制电力和接地平面噪声的方法

    公开(公告)号：US07778039B2

    公开(公告)日：2010-08-17

    申请号：US11430540

    申请日：2006-05-08

    Applicant: Houfei Chen ,  Shiyou Zhao

    Inventor： Houfei Chen ,  Shiyou Zhao

    IPC: H05K1/18

    CPC classification number: H05K1/0216 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09981 ,  H05K2203/0733 ,  Y10T29/4913 ,  Y10T29/49155

    Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

    Abstract translation: 具有电源和接地层的衬底，例如印刷电路板，包括至少一个噪声抑制结构，其被配置为抑制通过电力平面和接地平面中的至少一个传播的电波。 噪声抑制结构可以包括从功率平面大体上朝向接地平面延伸的电源平面延伸，以及从接地平面大致朝向电力平面延伸的接地平面延伸。 接地平面延伸部可以与动力平面延伸部分离距离小于分离动力和接地平面的距离。 电子器件组件和系统包括这样的衬底。 用于抑制电力平面和接地平面中的至少一个中的噪声的方法包括在电源和接地层之间提供这种噪声抑制结构。

    NON-COPLANAR HIGH-SPEED INTERCONNECTS
    56.
    发明申请
    NON-COPLANAR HIGH-SPEED INTERCONNECTS 有权
    非共享高速互联

    公开(公告)号：US20090033442A1

    公开(公告)日：2009-02-05

    申请号：US12248456

    申请日：2008-10-09

    Applicant: Yan Yang Zhao ,  Yuheng Lee ,  Jianying Zhou

    Inventor： Yan Yang Zhao ,  Yuheng Lee ,  Jianying Zhou

    IPC: H01P1/00

    CPC classification number: H01P5/028 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/10689

    Abstract: In one example embodiment, a high-speed package includes first and second layers and a multi-channel non-coplanar interconnect. The first layer includes first and second sets of coplanar transmission lines. The second layer includes third and fourth sets of coplanar transmission lines. The multi-channel non-coplanar interconnect includes first and second channels. The first channel connects the first set of transmission lines to the third set of transmission lines. The second channel connects the second set of transmission lines to the fourth set of transmission lines.

    Abstract translation: 在一个示例实施例中，高速封装包括第一和第二层以及多通道非共面互连。 第一层包括第一和第二组共面传输线。 第二层包括第三和第四组共面传输线。 多通道非共面互连包括第一和第二通道。 第一通道将第一组传输线连接到第三组传输线。 第二通道将第二组传输线连接到第四组传输线。

    WIRING STRUCTURE OF LAMINATED CAPACITORS
    57.
    发明申请
    WIRING STRUCTURE OF LAMINATED CAPACITORS 有权
    层压电容器接线结构

    公开(公告)号：US20080239622A1

    公开(公告)日：2008-10-02

    申请号：US11950381

    申请日：2007-12-04

    Applicant: Chien-Min HSU ,  Shih-Hsien WU ,  Min-Lin LEE ,  Shinn-Juh LAI

    Inventor： Chien-Min HSU ,  Shih-Hsien WU ,  Min-Lin LEE ,  Shinn-Juh LAI

    IPC: H01G4/236 ,  H05K1/16

    CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

    Abstract translation: 本发明涉及一种用于降低层叠电容器的等效串联电感（ESL）的布线结构。 层叠电容器包括多个导电层，沿层叠电容器的厚度方向延伸的电力通孔，并且从顶部导电层延伸至底部导电层，沿着层叠电容器的厚度方向延伸的接地通孔 并布置成从顶部导电层延伸到底部导电层。 导电层包括一组第一导电层和一组第二导电层。 电源通孔电耦合到第一导电层，并且接地通孔电耦合到第二导电层。 层叠电容器还包括电源通孔和接地通孔之间的补充通路。 补充通孔的长度要短于电源通孔和接地通孔。 辅助通孔电耦合到第一导电层和第二导电层之一。

    ELECTRONIC DEVICE AND RF MODULE
    58.
    发明申请
    ELECTRONIC DEVICE AND RF MODULE 审中-公开
    电子设备和射频模块

    公开(公告)号：US20080136559A1

    公开(公告)日：2008-06-12

    申请号：US11951600

    申请日：2007-12-06

    Applicant: Wataru TAKAHASHI ,  Shigeru Tsuchida ,  Hiroshi Okabe

    Inventor： Wataru TAKAHASHI ,  Shigeru Tsuchida ,  Hiroshi Okabe

    IPC: H03H7/00 ,  H04B1/02

    CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01L2924/0002 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/383 ,  H03H7/465 ,  H03H2001/0085 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

    Abstract: A parallel resonant circuit is realized by stacking first to fourth wiring patterns each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node and the other thereof is set to a signal output node. Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

    Abstract translation: 通过堆叠至少具有电感元件的第一至第四布线图案来实现并联谐振电路。 相邻的第一和第二布线图案中的一个设置为信号输入节点，另一个被设置为信号输出节点。 然后，信号输入节点通过第一布线图案，第三布线图案，第四布线图案和第二布线图案的电感元件依次连接到信号输出节点。 通过相互形成信号输入和输出节点的布线层，输入和输出节点之间的电容值与分离时相比增加。 此外，通过增加第一和第二布线图案的线宽，可以进一步提高电容值。 因此，可以在小面积上实现大的电容值，并且可以实现电子设备的小型化。

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