公开(公告)号：US07576438B2

公开(公告)日：2009-08-18

申请号：US11486064

申请日：2006-07-14

Applicant: Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

Inventor： Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/282 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/16503 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0391 ,  H05K2201/0989 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.

公开(公告)号：US20090196003A1

公开(公告)日：2009-08-06

申请号：US12362670

申请日：2009-01-30

Applicant: Seiya FUJII

Inventor： Seiya FUJII

IPC: H05K7/00 ,  H05K1/11 ,  C23F1/00 ,  H01L21/98 ,  H05K1/16

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09745 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land.

Abstract translation: 在根据本发明的布线板中，基板，设置在基板上的阻焊剂，焊盘，布线和连接布线和焊盘的连接部分，连接部分设置有作为 非平坦部分，并且形成为包括大于布线的宽度的宽度并且小于焊盘的宽度（直径），连接部分的宽度从布线向着平台逐渐增加。

公开(公告)号：US20090195935A1

公开(公告)日：2009-08-06

申请号：US12179786

申请日：2008-07-25

Applicant: Ho-joong CHOI

Inventor： Ho-joong CHOI

IPC: G11B5/48

CPC classification number: G11B5/4853 ,  H05K1/0216 ,  H05K1/056 ,  H05K3/28 ,  H05K2201/09236 ,  H05K2201/0989

Abstract: A suspension interconnect of a head gimbal assembly (HGA) includes a ground layer; a base layer formed of a dielectric material and disposed on the ground layer; a pair of read traces and a pair of write traces which are formed of a conductive material, disposed on the base layer to extend so as not to short each other; and a cover layer which are formed of a dielectric material, disposed on the base layer and the traces and are to seal the traces, wherein the cover layer includes a read cover layer which is to seal the read traces, and a write cover layer which is separated from the read cover layer and to seal the write traces.

Abstract translation: 头万向节组件（HGA）的悬挂互连包括接地层; 由介电材料形成并设置在接地层上的基层; 一对读取迹线和由导电材料形成的一对写入迹线，其设置在基底层上以便彼此不彼此缩短; 以及覆盖层，其由介电材料形成，设置在基底层和迹线上并且用于密封迹线，其中覆盖层包括用于密封读取的迹线的读取覆盖层和写入覆盖层， 与读取覆盖层分离并密封写入轨迹。

公开(公告)号：US20090189271A1

公开(公告)日：2009-07-30

申请号：US12352056

申请日：2009-01-12

Applicant: Soon-yong HUR ,  Mo-rae Kim ,  Hyeong-seob Kim

Inventor： Soon-yong HUR ,  Mo-rae Kim ,  Hyeong-seob Kim

IPC: H01L23/498

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package. The semiconductor package includes a substrate having a first surface and a second surface, a semiconductor chip mounted on the first surface of the substrate, at least one land disposed on the second surface of the substrate, and whose circumference includes a plurality of first group arcs, a mask layer covering the second surface of the substrate and including at least one opening that exposes the at least one land, and at least one external terminal disposed on the at least one land, wherein a portion of the at least one land is covered by the mask layer, and a sidewall of another portion of the at least one land is exposed by the at least one opening, and the circumference of the at least one opening includes a plurality of second group arcs, and a radius of the outermost arc from among the plurality of first group arcs is equal to a radius of the outermost arc from among the plurality of second group arcs.

Abstract translation: 一种印刷电路板，其使用大容量半导体芯片，半导体封装和卡的封装以及使用半导体封装的系统提供高可靠性。 半导体封装包括具有第一表面和第二表面的衬底，安装在衬底的第一表面上的半导体芯片，设置在衬底的第二表面上的至少一个焊盘，并且其周边包括多个第一组弧 覆盖基板的第二表面并包括暴露至少一个焊盘的至少一个开口的掩模层和设置在至少一个焊盘上的至少一个外部端子，其中所述至少一个焊盘的一部分被覆盖 并且所述至少一个平台的另一部分的侧壁被所述至少一个开口暴露，并且所述至少一个开口的圆周包括多个第二组弧，并且所述最外弧的半径 多个第一组弧之间的距离等于多个第二组弧之中的最外弧的半径。

公开(公告)号：US20090184413A1

公开(公告)日：2009-07-23

申请号：US12212089

申请日：2008-09-17

Applicant: Kazuaki TATSUMI ,  Yoshiki SOTA

Inventor： Kazuaki TATSUMI ,  Yoshiki SOTA

IPC: H01L23/498 ,  H05K1/05 ,  H01L21/50

CPC classification number: H05K3/3452 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/0094 ,  H05K3/427 ,  H05K2201/0959 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0585 ,  H05K2203/1178 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.

Abstract translation: 本发明的绝缘布线基板，其两面被阻焊剂覆盖，包括穿过绝缘布线板的半导体芯片安装区域中的至少一个通路孔，其中导体层经由所述导电层彼此电连接 至少一个通孔。 此外，除了穿过绝缘布线板的所述至少一个通孔之外，用阻焊剂覆盖安装区域。 因此，可以实现防止由于板吸收的水分的加热而发生的膨胀引起的缺陷的绝缘布线板以及减少不能提供布线的区域。

公开(公告)号：US20090179333A1

公开(公告)日：2009-07-16

申请号：US11972793

申请日：2008-01-11

Applicant: Alfred Martin ,  Barbara Hasler ,  Martin Franosch ,  Klaus-Guenter Oppermann

Inventor： Alfred Martin ,  Barbara Hasler ,  Martin Franosch ,  Klaus-Guenter Oppermann

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/3452 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06136 ,  H01L2224/10125 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/8109 ,  H01L2224/81205 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3484 ,  H05K2201/0989 ,  H05K2201/2081 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.

Abstract translation: 一种集成电路，包括衬底和衬底上的结构化层。 所述结构化层包括到所述衬底的开口，所述衬底上的第一场和第二场，其中所述第一场和所述第二场至少部分地与所述开口重叠。 集成电路还包括第一场区域中的第一材料和第二场区域中的第二材料。 第一种材料阻碍焊料材料的润湿，第二种材料通过焊料材料而被润湿。

公开(公告)号：US07553750B2

公开(公告)日：2009-06-30

申请号：US11559576

申请日：2006-11-14

Applicant: Chao Wen Shih

Inventor： Chao Wen Shih

IPC: H01L21/44

CPC classification number: H05K3/243 ,  H01L21/4853 ,  H05K1/111 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0391 ,  H05K2201/09436 ,  H05K2201/0989 ,  H05K2203/054

Abstract: A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of first and second electrically conductive pads; forming on the circuit board an insulating protection layer having a plurality of openings for exposing the first and second electrically conductive pads; forming a metal adhesive layer on the first and second electrically conductive pads; forming a conductive layer on the insulating protection layer and on the metal adhesive layer formed on the first and second electrically conductive pads, the conductive layer being electrical conductive to the first and second electrically conductive pads; forming on the conductive layer a resist layer having a plurality of openings for exposing the conductive layer on the second electrically conductive pads; and electroplating a conductive structure on the conductive layer on the second electrically conductive pads exposed from the openings.

Abstract translation: 公开了一种用于制造电路板的导电结构的方法。 该方法包括提供具有多个第一和第二导电焊盘的电路板; 在所述电路板上形成具有用于暴露所述第一和第二导电焊盘的多个开口的绝缘保护层; 在第一和第二导电焊盘上形成金属粘合剂层; 在绝缘保护层和形成在第一和第二导电焊盘上的金属粘合剂层上形成导电层，导电层与第一和第二导电焊盘导电; 在所述导电层上形成具有多个开口的抗蚀剂层，用于将所述导电层暴露在所述第二导电焊盘上; 以及在从所述开口暴露的所述第二导电焊盘上的所述导电层上电镀导电结构。

公开(公告)号：US20090152716A1

公开(公告)日：2009-06-18

申请号：US12330946

申请日：2008-12-09

Applicant: Tsuyoshi Sohara

Inventor： Tsuyoshi Sohara

IPC: H01L23/48 ,  H01L23/488

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/05599

Abstract: A wiring substrate on which an electronic component is flip-chip bonded, including a substrate main body, a solder resist which is formed on the substrate main body and having an opening, and a plurality of conductive pattern formed on the substrate main body, including exposure surfaces exposed from the opening of the solder resist. The conductive patterns include, a narrow interval group, a wide interval group, an interval between the adjacent conductive patterns belonging to the narrow interval group is narrower than an interval between the adjacent conductive patterns belonging to the wide interval group, an exposure length of the conductive patterns of the narrow interval group is shorter than an exposure length of the conductive patterns of the wide interval group.

Abstract translation: 包括基板主体，形成在基板主体上并具有开口的阻焊剂和形成在基板主体上的多个导电图案的电子部件倒装芯片接合的布线基板，包括： 从阻焊剂的开口露出的曝光表面。 导电图案包括窄间隔组，宽间隔组，属于窄间隔组的相邻导电图案之间的间隔比属于宽间隔组的相邻导电图案之间的间隔窄， 窄间隔组的导电图案比宽间隔组的导电图案的曝光长度短。

公开(公告)号：US20090117458A1

公开(公告)日：2009-05-07

申请号：US12285243

申请日：2008-09-30

Applicant: Chang-Yong Yun

Inventor： Chang-Yong Yun

IPC: H01M6/42 ,  H05K1/00 ,  H05K3/36

CPC classification number: H01M10/42 ,  H01M2/1061 ,  H01M2/30 ,  H01M10/425 ,  H01M2200/00 ,  H05K1/148 ,  H05K3/281 ,  H05K3/363 ,  H05K2201/0397 ,  H05K2201/0989 ,  Y10T29/49126

Abstract: A flexible Printed Circuit (PC) board, junction method thereof and battery pack using the flexible PC board prevents cracking of terminal units of a flexible PC board and reducing degradation thereof due to deformation by increasing its tensile strength. The flexible PC board has a multi-layered structure including wiring with terminal units, a first insulating layer and a second insulating layer arranged both over and under the wiring. An end of the second insulating layer is arranged between an end of the terminal units and an end of the first insulating layer.

Abstract translation: 使用柔性PC板的柔性印刷电路板（PC）板，其接合方法和电池组可防止柔性PC板的端子单元的破裂，并通过增加其拉伸强度来减少由于变形引起的劣化。 柔性PC板具有多层结构，包括布线与端子单元，第一绝缘层和布置在布线下方的第二绝缘层。 第二绝缘层的端部设置在端子单元的端部和第一绝缘层的端部之间。

公开(公告)号：US20090103274A1

公开(公告)日：2009-04-23

申请号：US11917613

申请日：2006-06-23

Applicant: R.W.J. Van Den Boomen

Inventor： R.W.J. Van Den Boomen

IPC: H05K1/02 ,  G06F17/50 ,  H05K7/20

CPC classification number: H05K3/3452 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/544 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19105 ,  H05K1/0203 ,  H05K1/0271 ,  H05K3/284 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2224/0401

Abstract: Consistent with an example embodiment, there is an apparatus comprising a circuit (500) board. The circuit board includes a first surface (501a) and a second surface (501b). The first and second surfaces each have at least a component populated thereon; the circuit board has a first surface thereof populated before a second surface thereof and is overmolded. The circuit board has conductive material disposed over areas of the second surface defining at least a feature (504) on the second surface. The at least a feature is defined by the conductive material and other than defined by solder resist (508) disposed on the second surface overlapping the conductive material, wherein the at least a feature is a feature for remaining exposed during a process of populating the first surface other than a fiducial.

Abstract translation: 与示例性实施例一致，存在包括电路（500）板的装置。 电路板包括第一表面（501a）和第二表面（501b）。 第一和第二表面各自具有至少一个填充在其上的部件; 电路板的第一表面在其第二表面之前填充并被包覆成型。 电路板具有布置在第二表面的区域上的导电材料，其限定了第二表面上的至少一个特征（504）。 所述至少一个特征由导电材料限定，而不是由设置在与导电材料重叠的第二表面上的阻焊剂（508）限定，其中至少一个特征是在填充第一 表面除了基准。