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    High voltage switching circuitry for a cross-point array
    61.
    发明授权
    High voltage switching circuitry for a cross-point array 有权
    用于交叉点阵列的高压开关电路

    公开(公告)号：US09047928B2

    公开(公告)日：2015-06-02

    申请号：US14312022

    申请日：2014-06-23

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Chang Hua Siau

    IPC: G11C11/34 ,  G11C8/08 ,  G11C13/00 ,  G11C8/10

    CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

    Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

    Abstract translation: 公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。 在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。 此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储器单元，其被配置为例如在大于第一电压范围的第二电压范围内操作 。 交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。 集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。 有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

    VERTICAL CROSS POINT ARRAYS FOR ULTRA HIGH DENSITY MEMORY APPLICATIONS
    63.
    发明申请
    VERTICAL CROSS POINT ARRAYS FOR ULTRA HIGH DENSITY MEMORY APPLICATIONS 有权
    用于超高密度存储器应用的垂直交点点阵列

    公开(公告)号：US20150097155A1

    公开(公告)日：2015-04-09

    申请号：US14568802

    申请日：2014-12-12

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Bruce Lynn Bateman

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    Abstract translation: 超高密度垂直交叉点阵列包括多个水平线层，水平线与以行和列排列的多条垂直线交错。 垂直线与水平线交错，使得一行垂直线位于每条水平线层中每条连续的一对水平线之间。 每个垂直线包括由单层或多层记忆膜包围的中心导体。 因此，当与水平线交错时，两端存储单元一体地形成在每条垂直线的中心导体和每个交叉水平线之间。 通过配置垂直和水平线，使得一行垂直线位于每条连续的一对水平线之间，可以实现仅仅2F2的单位存储单元占用空间。

    HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY
    64.
    发明申请
    HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY 有权

    公开(公告)号：US20130308410A1

    公开(公告)日：2013-11-21

    申请号：US13693214

    申请日：2012-12-04

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Christophe Chevallier ,  Chang Hua Siau

    IPC: G11C8/08 ,  G11C8/10

    CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

    Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

    Providing a reference voltage to a cross point memory array
    66.
    发明申请
    Providing a reference voltage to a cross point memory array 有权
    向交叉点存储器阵列提供参考电压

    公开(公告)号：US20040160806A1

    公开(公告)日：2004-08-19

    申请号：US10330170

    申请日：2002-12-26

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

    IPC: G11C011/00

    CPC classification number: G11C13/0007 ,  G11C5/147 ,  G11C11/15 ,  G11C13/0004 ,  G11C2213/31

    Abstract: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array in order to prevent unselected conductive array lines from floating to an undesired voltage. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

    Abstract translation: 向交叉点存储器阵列提供参考电压。 本发明是一种交叉点存储器阵列和一些外围电路，当被激活时，它向交叉点阵列提供参考电压，以便防止未选择的导电阵列线漂浮到不需要的电压。 外围电路可在特定内存插头选择之前，之后或期间激​​活。 如果外围电路在选择期间被激活，则只有未选择的导电阵列线才能被带到参考电压。 否则，所有导电阵列线可以被带到参考电压。

    MULTI-OUTPUT MULTIPLEXOR
    67.
    发明申请
    MULTI-OUTPUT MULTIPLEXOR 有权
    多输出多路复用器

    公开(公告)号：US20040160805A1

    公开(公告)日：2004-08-19

    申请号：US10330150

    申请日：2002-12-26

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Christopher J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

    IPC: G11C011/00

    CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

    Abstract: Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the mulitplexor's ports., A modulating circuit can be fully turned on, partially turned on, or fully turned off. In a preferred embodiment, a gate circuit is in electrical contact with ground such that when the gate circuit is turned on and its associated modulating circuit is not passing voltage, the multiplexor output associated with the modulating circuit goes to ground.

    Abstract translation: 提供多输出多路复用器。 本发明是多输出多路复用器，其根据控制信号允许各种调制电路不通过电压，传递一些电压或通过多路复用器端口之一上的所有电压。调制电路可以完全打开，部分地 打开或完全关闭。 在优选实施例中，门电路与接地电接触，使得当门电路接通并且其相关联的调制电路不通过电压时，与调制电路相关联的多路复用器输出接地。

    Adaptive programming technique for a re-writable conductive memory device
    68.
    发明申请
    Adaptive programming technique for a re-writable conductive memory device 有权
    用于可重写导电存储器件的自适应编程技术

    公开(公告)号：US20040160798A1

    公开(公告)日：2004-08-19

    申请号：US10680508

    申请日：2003-10-06

    Applicant: Unity Semiconductor Inc.

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier

    IPC: G11C017/00

    CPC classification number: G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3468 ,  G11C2013/0066 ,  G11C2213/31

    Abstract: A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the programming circuit can be used to only program the memory cell when it has a value that needs to be changed.

    Abstract translation: 提供了编程电路。 由于导电存储单元被编程，其电阻变化。 所提供的编程电路在编程存储器单元时监视变化的电阻。 只要编程实际需要，编程电路就可以用于只对存储单元进行编程。 此外，编程电路可以用于仅当存储单元具有需要改变的值时对其进行编程。

    Vertical cross-point arrays for ultra-high-density memory applications
    70.
    发明授权
    Vertical cross-point arrays for ultra-high-density memory applications 有权

    公开(公告)号：US11849593B2

    公开(公告)日：2023-12-19

    申请号：US17840385

    申请日：2022-06-14

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L45/00 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

    CPC classification number: H10B63/845 ,  H10B63/22 ,  H10B63/34 ,  H10N70/24 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8833 ,  H10N70/8836

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

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