公开(公告)号：US20170086288A1

公开(公告)日：2017-03-23

申请号：US14862159

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Gong Ouyang ,  Shaowu Huang ,  Kai Xiao

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H01P3/08 ,  H01P11/00

CPC classification number: H01P3/081 ,  H01P3/04 ,  H01P11/003 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09036 ,  H05K2201/09872

Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.

公开(公告)号：US20170019105A1

公开(公告)日：2017-01-19

申请号：US14865682

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Zuoguo Wu ,  Venkatraman Iyer

IPC: H03K19/0175 ,  H03K5/08

CPC classification number: H03K19/017509 ,  G06F13/00 ,  H03K5/08 ,  H04L25/0272

Abstract: A redriver device is provided to receive signals from a first device and forward the signals to a second device on a differential link. Detection circuitry is provided to detect presence of the second device on the link by detecting a pulldown voltage generated from termination of the second device on the link, and pulldown relay circuitry is provided to generate an emulated version of the pulldown voltage of the second device on pins to connect to the first device in response to detecting presence of the second device on the link.

Abstract translation: 提供转接装置以从第一装置接收信号，并将信号转发到差分链路上的第二装置。 提供检测电路以通过检测从链路上的第二设备的终止产生的下拉电压来检测链路上的第二设备的存在，并且提供下拉继电器电路以产生第二设备的下拉电压的仿真版本 以响应于检测到链路上的第二设备的存在而连接到第一设备的引脚。

公开(公告)号：US20170006698A1

公开(公告)日：2017-01-05

申请号：US15265704

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H01P1/24 ,  H05K1/18 ,  H05K3/40 ,  H05K3/22 ,  H01P3/08 ,  H01P11/00 ,  H01R12/73 ,  H01R13/6461 ,  H05K1/02 ,  H01P1/26

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160276091A1

公开(公告)日：2016-09-22

申请号：US14664827

申请日：2015-03-21

Applicant: INTEL CORPORATION

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

IPC: H01F27/28 ,  H05K3/30 ,  H05K1/11 ,  H01F41/04 ,  H05K1/18

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/0233 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/165

Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

公开(公告)号：US20240355759A1

公开(公告)日：2024-10-24

申请号：US18136775

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Phil Geng ,  Baris Bicen ,  Kai Xiao ,  Sanjoy Saha ,  Prasanna Raghavan

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3675 ,  H01L23/4006 ,  H01L2023/4081 ,  H01L2023/4087 ,  H01L23/427 ,  H01L24/32 ,  H01L24/71 ,  H01L2224/32245 ,  H01L2224/71

Abstract: Damping structures in integrated circuit (IC) devices, and techniques for forming the structures are discussed. An IC device includes, between an IC package and a socket, both a spring force and a damping structure adjacent an array of pins and corresponding lands. The damping structure may be of a dissipative, viscous, or viscoelastic material. The damping structure may be between the IC package and socket. The damping structure may be within a periphery of the socket. The damping structure may be coupled to the IC package or the socket by an adhesive or a press fit. A heatsink or a heat spreader may be coupled to the IC package over the socket.

公开(公告)号：US11900523B2

公开(公告)日：2024-02-13

申请号：US17505387

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Michael Apodaca ,  Carson Brownlee ,  Thomas Raoux ,  Joshua Barczak ,  Gabor Liktor

IPC: G06T15/06 ,  G06T1/20

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T2200/04

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

公开(公告)号：US20240004713A1

公开(公告)日：2024-01-04

申请号：US18363339

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU ,  Joydeep RAY ,  Kamal SINHA ,  Prasoonkumar SURTI ,  Kiran C. VEERNAPU ,  Subramaniam MAIYURAN ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F1/329 ,  G06F9/4893 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  Y02D10/00 ,  G06T2200/28

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US11829525B2

公开(公告)日：2023-11-28

申请号：US17233649

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  James M. Holland ,  Pattabhiraman K ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Kamal Sinha ,  Ankur N. Shah ,  Deepak S. Vembar ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F3/01 ,  G06T15/00 ,  G06T3/40 ,  G06T1/60 ,  G06F3/16 ,  G06F3/147 ,  G06T19/00 ,  G06F3/04815 ,  G06T7/80

CPC classification number: G06F3/013 ,  G06F3/011 ,  G06F3/016 ,  G06F3/04815 ,  G06F3/147 ,  G06F3/167 ,  G06T1/60 ,  G06T3/40 ,  G06T7/80 ,  G06T15/005 ,  G06T19/006 ,  G06T2200/28

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

公开(公告)号：US20230380067A1

公开(公告)日：2023-11-23

申请号：US17750016

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Kai Xiao ,  Carlos Alberto Lizalde Moreno ,  Luis E. Rosales Galvan

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H05K2201/10325 ,  H05K2201/10303 ,  H05K2201/10704

Abstract: In one embodiment, a package substrate or main circuit board includes electrical connectors arranged in a compressed array pattern, wherein a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions. The array pattern may be hexagonal or rectangular, and differential pairs of the electrical connectors may be arranged in the direction of compression.

公开(公告)号：US11527035B2

公开(公告)日：2022-12-13

申请号：US17308828

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Carson Brownlee ,  Gabor Liktor ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux

IPC: G06T15/06 ,  G06T15/80 ,  G06T15/04

Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.