公开(公告)号：US11031360B2

公开(公告)日：2021-06-08

申请号：US16990782

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H05K1/16 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10705293B2

公开(公告)日：2020-07-07

申请号：US16061540

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Rahul Jain ,  Sri Ranga Sai Boyapati ,  Maroun Moussallem ,  Rahul N. Manepalli ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/132 ,  H01P5/107 ,  G02B6/134 ,  G02B6/12

Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.

公开(公告)号：US10672695B2

公开(公告)日：2020-06-02

申请号：US16061890

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Rahul N. Manepalli

IPC: H01L23/498 ,  H01L23/373 ,  H01L21/48 ,  H01L23/28

Abstract: This document discusses, among other things, a multi-layer molded substrate having layers with a graded coefficients of thermal expansions (CTEs) to optimize thermal performance of the multi-layer molded substrate with first and second structures attached to top and bottom surfaces of the multi-layer molded substrate, respectively.

公开(公告)号：US10658281B2

公开(公告)日：2020-05-19

申请号：US15721321

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20190385959A1

公开(公告)日：2019-12-19

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822 ,  H01L27/04 ,  H01F27/28 ,  H01F27/24

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10431537B1

公开(公告)日：2019-10-01

申请号：US16014134

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20190103348A1

公开(公告)日：2019-04-04

申请号：US15721321

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20160284630A1

公开(公告)日：2016-09-29

申请号：US14653033

申请日：2014-07-11

Applicant: INTEL CORPORATION

Inventor： Alejandro Levander ,  Tatyana Andryushchenko ,  David Staines ,  Mauro Kobrinsky ,  Aleksandar Aleksov ,  Dilan Seneviratne ,  Javier Soto Gonzalez ,  Srinivas Pietambaram ,  Rafiqul Islam

IPC: H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/4985 ,  B23B5/16 ,  B32B27/08 ,  B32B27/283 ,  B32B2307/54 ,  B32B2307/7265 ,  B32B2439/00 ,  B32B2457/00 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/48227 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0715 ,  H01L2924/15747 ,  H01L2924/15791 ,  H05K1/0283 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

Abstract translation: 这里通常讨论的是可以包括可拉伸和可弯曲装置的系统和方法。 根据一个实例，一种方法可以包括（1）在面板上沉积第一弹性体材料，（2）在弹性体材料上层叠微量材料，（3）处理微量材料以将痕量材料图案化成一个或多个迹线 或更多的接合垫，（4）将管芯附接到所述一个或多个接合焊盘，或（5）在所述一个或多个迹线上和周围沉积第二弹性体材料，所述接合焊盘和所述管芯以将所述一个或多个 迹线和第一和第二弹性体材料中的一个或多个接合焊盘。

公开(公告)号：US12272656B2

公开(公告)日：2025-04-08

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.