公开(公告)号：US09639419B2

公开(公告)日：2017-05-02

申请号：US14745472

申请日：2015-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: H03M13/09 ,  G06F11/10 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50

CPC classification number: G06F11/1048 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/5004

Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.

公开(公告)号：US09607704B2

公开(公告)日：2017-03-28

申请号：US14682123

申请日：2015-04-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C29/00 ,  G11C16/26 ,  G06F11/10 ,  G11C7/10 ,  G11C29/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C2029/0411

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

公开(公告)号：US09530509B2

公开(公告)日：2016-12-27

申请号：US14727878

申请日：2015-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Chi-Heng Yang

IPC: G06F12/00 ,  G11C16/14 ,  G06F3/06 ,  G06F12/08 ,  G11C16/26 ,  G11C29/44

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2211/5648

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.

Abstract translation: 提供数据编程方法，存储器存储装置和存储器控制电路单元。 该方法包括：接收第一数据并将第一数据编程到第一较低物理编程单元中; 接收第二数据; 响应于要被编程到与第一下部物理编程单元相对应的第一上部物理编程单元的第二数据，执行不包括通过使用默认读取电压读取第一下部物理编程单元的第一数据获取操作; 以及根据通过第一数据获取操作获得的第三数据将第二数据编程到第一上层物理编程单元中。

公开(公告)号：US09349475B2

公开(公告)日：2016-05-24

申请号：US14156477

申请日：2014-01-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu

IPC: G06F12/00 ,  G11C16/32 ,  G11C16/26 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/32 ,  G06F3/0619 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/349

Abstract: A time estimating method, a memory storage device, and a memory controlling circuit unit are provided for a rewritable non-volatile memory module having memory cells. The method includes: writing first data into first memory cells of the memory cells; reading the first memory cells according to a reading voltage, so as to determine whether each of the first memory cells belongs to a first state or a second state; and calculating a quantity of the first memory cells belonging to the first state, and obtaining a time information of the rewritable non-volatile memory module according to the quantity.

Abstract translation: 为具有存储单元的可重写非易失性存储器模块提供时间估计方法，存储器存储装置和存储器控制电路单元。 该方法包括：将第一数据写入存储器单元的第一存储单元; 根据读取电压读取第一存储器单元，以便确定每个第一存储器单元是否属于第一状态或第二状态; 以及计算属于所述第一状态的所述第一存储单元的数量，以及根据所述数量获得所述可重写非易失性存储器模块的时间信息。

公开(公告)号：US20160098316A1

公开(公告)日：2016-04-07

申请号：US14565437

申请日：2014-12-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Shao-Wei Yen ,  Tien-Ching Wang ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Li-Chun Liang

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.

Abstract translation: 提供了一种用于可重写非易失性存储器模块，存储器存储装置和存储器控制电路单元的错误处理方法。 可重写非易失性存储器模块包括多个存储单元。 该错误处理方法包括：从存储器单元发送用于读取多个位的第一读取命令序列; 对比特执行第一解码; 如果所述比特具有至少一个错误，则确定每个错误是否属于第一类型错误或第二类型错误; 如果所述第一错误属于所述第一类型错误，则记录所述至少一个错误中的第一错误的相关信息; 并且如果第一错误属于第二类型错误，则不记录第一错误的相关信息。 因此，可以适当地处理特定类型的错误。

公开(公告)号：US09257187B2

公开(公告)日：2016-02-09

申请号：US14285656

申请日：2014-05-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Kiang-Giap Lau ,  Hoe-Hong Lim ,  Yu-Cheng Hsu

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C7/02 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: A data writing method, and a memory control circuit unit and a memory storage apparatus using the method are provided. The method including: programming data to several memory cells on a first word line of the rewritable non-volatile memory module of the memory storage apparatus, and a first predetermined reading voltage is initially configured for the first word line. The data storing method further includes: adjusting the first predetermined reading voltage to obtain a first available reading voltage for the first word line, and applying the first available reading voltage to the first word line to read first page data. The storing method further includes: if the difference value between the first available reading voltage and the first predetermined reading voltage is larger than a predetermined threshold value, performing a protection operation for the first page data.

Abstract translation: 提供一种数据写入方法，以及存储器控制电路单元和使用该方法的存储器存储装置。 该方法包括：将数据编程到存储器存储装置的可重写非易失性存储器模块的第一字线上的多个存储单元，并且首先为第一字线配置第一预定读取电压。 数据存储方法还包括：调整第一预定读取电压以获得第一字线的第一可用读取电压，以及将第一可用读取电压施加到第一字线以读取第一页数据。 存储方法还包括：如果第一可用读取电压和第一预定读取电压之间的差值大于预定阈值，则执行第一页数据的保护操作。

公开(公告)号：US20150293813A1

公开(公告)日：2015-10-15

申请号：US14296383

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/37

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/3746

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元，该解码方法包括：根据硬判定电压读取多个存储单元以获得硬比特; 对所述硬比特执行奇偶校验处理以获得多个综合征; 根据综合征确定硬比特是否有错误; 如果硬比特错误，则根据与硬比特相对应的硬比特和综合征权重信息的信道信息更新硬比特。

公开(公告)号：US20150293811A1

公开(公告)日：2015-10-15

申请号：US14295355

申请日：2014-06-04

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US09136875B2

公开(公告)日：2015-09-15

申请号：US14054848

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Wei Yen ,  Yu-Hsiang Lin ,  Wei Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10 ,  H03M13/11

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6577

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract translation: 提供了解码方法，存储器存储装置和可重写非易失性存储器模块。 该方法包括：根据读取电压从可重写非易失性存储器模块读取多个位; 对比特执行低密度奇偶校验（LDPC）算法的奇偶校验以获得校正子，并且每个比特对应于至少一个综合征; 确定所述位是否具有根据所述综合征的错误; 如果这些比特具有错误，则根据与每个比特对应的校验子获得每个比特的综合征权重; 根据每个位的校正子权重获得每个比特的初始值; 以及根据初始值对该比特执行LDPC算法的第一迭代解码。 因此，解码速度增加。

公开(公告)号：US09123418B2

公开(公告)日：2015-09-01

申请号：US14269212

申请日：2014-05-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Riichiro Shirota ,  Nina Mitiukhina ,  Tsai-Hao Kuo

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor.

Abstract translation: 描述了NAND​​闪存单元，其包括串联连接的一串存储器单元，耦合到串的两个端子的S / D区，串的端子与S / D区之间的至少一个选择晶体管耦合，以及 所述至少一个擦除晶体管耦合在所述至少一个选择晶体管和S / D区之间。 选择晶体管用于选择存储单元串。 擦除晶体管用于减小选择晶体管的Vt-偏移。