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    Three-dimensional memory devices
    61.
    发明授权
    Three-dimensional memory devices 有权

    公开(公告)号：US11158622B1

    公开(公告)日：2021-10-26

    申请号：US17020416

    申请日：2020-09-14

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Kun Zhang

    IPC: H01L25/18 ,  G11C16/14 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L25/00

    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, an N-well in the P-type doped semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the P-type doped semiconductor layer, a first source contact above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact above the memory stack and in contact with the N-well.

    Three-dimensional memory devices and methods for forming the same
    64.
    发明授权
    Three-dimensional memory devices and methods for forming the same 有权

    公开(公告)号：US12300648B2

    公开(公告)日：2025-05-13

    申请号：US17481943

    申请日：2021-09-22

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Yuancheng Yang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Liang Chen ,  Yanhong Wang ,  Wei Liu

    IPC: H10B43/20 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/50

    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

    Three-dimensional NAND memory and fabrication method thereof
    65.
    发明授权
    Three-dimensional NAND memory and fabrication method thereof 有权

    公开(公告)号：US12283322B2

    公开(公告)日：2025-04-22

    申请号：US17705983

    申请日：2022-03-28

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Linchun Wu ,  Kun Zhang ,  Wenxi Zhou

    IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

    THREE-DIMENSIONAL MEMORY AND FABRICATION METHOD THEREOF, MEMORY SYSTEM AND ELECTRONIC APPARATUS
    68.
    发明申请
    THREE-DIMENSIONAL MEMORY AND FABRICATION METHOD THEREOF, MEMORY SYSTEM AND ELECTRONIC APPARATUS 有权

    公开(公告)号：US20240431100A1

    公开(公告)日：2024-12-26

    申请号：US18824538

    申请日：2024-09-04

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Zhong Zhang ,  Di Wang ,  Wenxi Zhou ,  Kun Zhang ,  Zhiliang Xia ,  Zongliang Huo

    IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    Abstract: The present disclosure provides a three-dimensional (3D) memory. The 3D memory may include a stack structure including gate layers and dielectric layers disposed alternately. The stack structure may include a step structure including a plurality of staircase structures disposed in a first direction and having different heights in a second direction. The 3D memory may include a plurality of first stops disposed in the first direction and located on the plurality of steps of at least one of the staircase structures, with each of the plurality of first stops disposed on the corresponding step of the plurality of steps. The 3D memory may include a protection layer covering the step structure and the first stops. The 3D memory may include a plurality of contact posts each extending through the protection layer and the first stop and being connected with the gate layer in the step corresponding to the first stop.

    Three-dimensional memory devices and methods for forming the same
    69.
    发明授权
    Three-dimensional memory devices and methods for forming the same 有权

    公开(公告)号：US12176309B2

    公开(公告)日：2024-12-24

    申请号：US17481875

    申请日：2021-09-22

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Yanhong Wang ,  Wei Liu ,  Liang Chen ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

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