公开(公告)号：US07501581B2

公开(公告)日：2009-03-10

申请号：US11634868

申请日：2006-12-07

Applicant: Yasuhito Funada ,  Jun Ishii

Inventor： Yasuhito Funada ,  Jun Ishii

IPC: H05K1/00

CPC classification number: H05K1/0269 ,  H05K1/056 ,  H05K3/44 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/0723

Abstract: A wired circuit board and a producing method thereof are provided which can precisely form an insulating layer and reduce transmission loss with a simple layer structure and also features excellent long-term reliability by preventing the occurrence of an ion migration phenomenon between a ground layer and a positioning mark layer, and the insulating layer to improve the adhesion therebetween and the conductivity of a conductor. A metal supporting board is prepared and a first metal thin film is formed on the metal supporting board. A resist is formed in a pattern and a ground layer and a positioning mark layer are formed on the first metal thin film exposed from the resist at the same time. A second metal thin film is formed over the ground layer and the positioning mark layer, then the resist is removed. An insulating base layer is formed on the first metal thin film including the upper surface of the second metal thin film, thereafter, a conductive pattern is formed on the insulating base layer.

公开(公告)号：US07499287B2

公开(公告)日：2009-03-03

申请号：US12015535

申请日：2008-01-17

Applicant: Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

Inventor： Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0243 ,  H01Q3/26 ,  H01Q21/0006 ,  H01Q21/0037 ,  H05K3/429 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/10553 ,  H05K2203/049 ,  Y10T29/49165

Abstract: A structural printed wiring board panel includes a multilayer printed wiring board having opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.

Abstract translation: 结构印刷线路板面板包括具有相对的外表面和层间互连的多层印刷线路板，其布置RF，功率和控制信号。 连接区域形成在至少一个面上或之上，用于连接层间互连和任何电气部件。 金属面板固定在至少一个外表面上，为多层印刷线路板增加结构刚性。 金属面板可以具有定位成允许接近连接区域的孔。 RF部件可以由面板承载并且可操作地连接到连接区域。 天线元件可以定位在相同或相对的面板上并且可操作地连接到RF部件以形成相控阵列印刷线路板（PWB）面板。

公开(公告)号：US07477194B2

公开(公告)日：2009-01-13

申请号：US11294039

申请日：2005-12-05

Applicant: James P. Coleman ,  Scott Wayne Ferguson ,  Jaime C. Grunlan ,  Ian J. Forster ,  Andrew W. Holman ,  Peikang Liu

Inventor： James P. Coleman ,  Scott Wayne Ferguson ,  Jaime C. Grunlan ,  Ian J. Forster ,  Andrew W. Holman ,  Peikang Liu

IPC: H01Q1/38

CPC classification number: H01L23/49855 ,  G06K19/07749 ,  H01L21/4846 ,  H01L24/95 ,  H01L2224/95085 ,  H05K1/095 ,  H05K1/165 ,  H05K3/205 ,  H05K3/32 ,  H05K3/386 ,  H05K2201/0347 ,  H05K2203/1469 ,  H05K2203/1545 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T156/1062

Abstract: A method of forming an electrically-conductive pattern includes selectively electroplating the top portions of a substrate that corresponds to the pattern, and separating the conductive pattern from the substrate. The electroplating may also include electrically connecting the conductive pattern to an electrical component. Conductive ink, such as ink including carbon particles, may be selectively placed on the conductive substrate to facilitate plating of the desired pattern and/or to facilitate separation of the pattern from the substrate. An example of a conductive pattern is an antenna for a radio-frequency identification (RFID) device such as a label or a tag. One example of an electrical component that may be electrically connected to the antenna, is an RFID strap or chip.

Abstract translation: 形成导电图案的方法包括选择性地电镀对应于图案的衬底的顶部部分，并且将导电图案与衬底分离。 电镀还可以包括将导电图案电连接到电气部件。 诸如包含碳颗粒的墨的导电油墨可以选择性地放置在导电基底上，以便于电镀所需图案和/或促进图案与基底的分离。 导电图案的示例是用于诸如标签或标签的射频识别（RFID）设备的天线。 可以电连接到天线的电气部件的一个例子是RFID带或芯片。

公开(公告)号：US20080277155A1

公开(公告)日：2008-11-13

申请号：US12078514

申请日：2008-04-01

Applicant: Akio Horiuchi

Inventor： Akio Horiuchi

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K3/4647 ,  H05K1/115 ,  H05K3/243 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a method of manufacturing a wiring substrate of the present invention, a through-hole plating layer is formed from an inner surface of a through hole in a substrate to both surface sides, then a resin is filled in a through hole, and then a first resist in which an opening portion is provided on the through hole is formed. Then, a partial cover plating layer is formed in the opening portion in the first resist, then the first resist is removed, and then a second resist that covers a whole of the partial cover plating layer and has a pattern for patterning the through-hole plating layer is formed. Then, a pad wiring portion containing the partial cover plating layer and a wiring pattern are obtained by etching the through-hole plating layer while using the second resist as a mask.

Abstract translation: 在本发明的布线基板的制造方法中，从基板的贯通孔的内表面到两面形成通孔镀层，然后在通孔中填充树脂，然后将 形成在通孔上设置有开口部的第一抗蚀剂。 然后，在第一抗蚀剂的开口部分形成部分覆盖镀层，然后除去第一抗蚀剂，然后再覆盖覆盖整个部分覆盖镀层的第二抗蚀剂，并且具有用于图案化通孔的图案 形成镀层。 然后，通过在使用第二抗蚀剂作为掩模的同时蚀刻通孔镀层来获得包含部分覆盖层和布线图案的焊盘布线部分。

公开(公告)号：US20080206553A1

公开(公告)日：2008-08-28

申请号：US12066340

申请日：2006-08-31

Applicant: Norbert Schneider ,  Gerald Lippert ,  Rene Lochtman ,  Heiko Maas ,  Jurgen Pfister ,  Bettina Sobotka ,  Norbert Wagner

Inventor： Norbert Schneider ,  Gerald Lippert ,  Rene Lochtman ,  Heiko Maas ,  Jurgen Pfister ,  Bettina Sobotka ,  Norbert Wagner

IPC: B32B33/00 ,  C09D5/24 ,  C25D5/54 ,  B05D5/12

CPC classification number: H01B1/22 ,  C09D5/24 ,  H05K1/095 ,  H05K3/246 ,  H05K2201/0245 ,  H05K2201/0248 ,  H05K2201/0272 ,  H05K2201/0347 ,  Y10T428/25 ,  Y10T428/256 ,  Y10T428/258

Abstract: The present invention relates to a dispersion for application of a metal layer on a substrate that is not electrically conductive, comprising an organic binder component, a metal component with different metals and/or metal particle shapes, and with a solvent component. The invention moreover relates to a process for preparation of the dispersion, to a process using the dispersion for production of a metal layer, if appropriate structured, and to the resultant substrate surfaces and their use.

Abstract translation: 本发明涉及一种用于在不导电的基底上施加金属层的分散体，其包含有机粘合剂组分，具有不同金属和/或金属颗粒形状的金属组分以及溶剂组分。 本发明还涉及制备分散体的方法，使用该分散体制备金属层的方法，如果合适的结构，以及所得到的基材表面及其用途。

公开(公告)号：US07396885B2

公开(公告)日：2008-07-08

申请号：US10241459

申请日：2002-09-12

Applicant: Kiyoshi Sato ,  Kazunori Kitamura

Inventor： Kiyoshi Sato ,  Kazunori Kitamura

IPC: C08L63/10

CPC classification number: H05K3/0094 ,  C08F283/10 ,  C08F290/00 ,  C08F290/06 ,  C08F290/064 ,  C08L63/00 ,  C08L63/10 ,  G03F7/038 ,  H05K3/287 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  C08L2666/22

Abstract: A photo-setting and thermosetting resin composition comprises (I) a partial adduct of epoxy resin with unsaturated aliphatic acid, (II) (meth)acrylates, (III) a photocrosslinking agent, (IV) liquid epoxy resin, and (V) a latent curing agent. The resin composition can be easily charged and plugged into a through-hole, does not drip down, and can be effectively photo-set and thermoset. A photo-set product prepared of the resin composition can be easily polished. A plugged-through-hole printed wiring (substrate) board prepared of the resin composition does not cause defects such as hollows, cracks, blisters, peelings and so on, is excellent in solder-resistance, does not corrode a metal part, and can produce an appliance of high reliability and long life which does not occur short circuit and poor electrical connection.

Abstract translation: 光固性和热固性树脂组合物包含（I）环氧树脂与不饱和脂肪酸的部分加合物，（II）（甲基）丙烯酸酯，（III）光交联剂，（IV）液体环氧树脂和（V） 潜在固化剂。 树脂组合物可以容易地充填并堵塞到通孔中，不会滴落，并且可以有效地进行光固化和热固化。 可以容易地研磨由树脂组合物制备的光固化剂产品。 通过树脂组合物制成的通孔印刷布线（基板）板不会引起中空，裂纹，起泡，剥离等缺陷，耐焊接性优异，不会腐蚀金属部，能够 生产高可靠性，长寿命的电器，不会发生短路和电连接不良。

公开(公告)号：US07377030B2

公开(公告)日：2008-05-27

申请号：US11266480

申请日：2005-11-04

Applicant: Takashi Shuto ,  Kenji Takano ,  Kenji Ilda ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

Inventor： Takashi Shuto ,  Kenji Takano ,  Kenji Ilda ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

IPC: H05K3/36

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/183 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/068 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/016 ,  H05K2203/061 ,  H05K2203/085 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  H01L2224/0401

Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.

Abstract translation: 本发明涉及一种制造布线板的方法，包括：堆叠层，其中布线图案用绝缘层堆叠; 以及与所述堆积层分开形成的芯基板，所述方法包括以下步骤：在板状支撑体上可分离地形成所述堆积层; 将芯基板电连接到支撑体上的堆积层的布线图案; 并且从堆积层移除支撑体以形成其中堆积层连接到芯基板的布线板。 通过可分离地形成积层和芯基板，可以制造有效显示其特性的布线板。

公开(公告)号：US20080089046A1

公开(公告)日：2008-04-17

申请号：US11950436

申请日：2007-12-05

Applicant: Shinichi Sumi ,  Yutaka Iguchi

Inventor： Shinichi Sumi ,  Yutaka Iguchi

IPC: H05K7/00 ,  H05K1/02

CPC classification number: H05K3/4069 ,  H05K1/113 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2201/0394 ,  H05K2201/09909 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53548

Abstract: A printed wiring board for mounting electronic components includes an insulating layer and a wiring pattern formed on one surface of the insulating layer, wherein one end portion of a filled via is connected with the wiring pattern and the other end portion is overlaid with a covering layer obtained by applying a conductive paste to cover at least the boundary between the filled via and the insulating layer; alternatively, a plating resist is formed at the other end portion to cover at least the boundary between the filled via and the insulating layer, and is removed after an end portion of the filled via enclosed within the plating resist is plated to produce a terminal layer, thereby preventing a wet processing liquid such as a tin plating solution from leaking in between the filled via and the insulating layer.

Abstract translation: 一种用于安装电子部件的印刷电路板包括绝缘层和形成在绝缘层的一个表面上的布线图案，其中填充的通孔的一个端部与布线图案连接，另一个端部覆盖有覆盖层 通过施加导电膏以至少覆盖填充的通孔和绝缘层之间的边界获得; 或者，在另一端部形成电镀抗蚀剂，以至少覆盖填充的通孔和绝缘层之间的边界，并且在电镀抗蚀剂中包含的填充通孔的端部被电镀之后，将其去除以产生端层 从而防止诸如镀锡溶液之类的湿处理液体在填充的通孔和绝缘层之间泄漏。

公开(公告)号：US20080066304A1

公开(公告)日：2008-03-20

申请号：US11902758

申请日：2007-09-25

Applicant: Deepak Pai ,  Ronald Denny

Inventor： Deepak Pai ,  Ronald Denny

IPC: H05K3/34 ,  H05K3/00

CPC classification number: H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

Abstract translation: 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

公开(公告)号：US20080040920A1

公开(公告)日：2008-02-21

申请号：US11506707

申请日：2006-08-18

Applicant: Andrew J. Brackenbury ,  Lance A. Collier ,  Larry L. Galey ,  Nathan S. Moyer

Inventor： Andrew J. Brackenbury ,  Lance A. Collier ,  Larry L. Galey ,  Nathan S. Moyer

IPC: H05K1/03

CPC classification number: H05K1/167 ,  H05K3/246 ,  H05K3/4069 ,  H05K3/4611 ,  H05K2201/0347 ,  H05K2203/0191 ,  H05K2203/1476 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A multi-stage masking and plating process for making printed wiring boards with multiple interstitial resistors includes disposing a first mask over a printed wiring board substrate that leaves one or more first vias of the plurality of vias exposed and covers the remaining vias. The first vias are filled with an electrically resistive compound to thereby form one or more first interstitial resistors. The first mask is removed, and a second mask is disposed over the printed wiring board substrate that leaves one or more second vias of the plurality of vias exposed and covers the remaining vias. The second vias are filled with an electrically resistive compound to thereby form one or more second interstitial resistors. The second mask is then removed.

Abstract translation: 用于制造具有多个间隙电阻器的印刷线路板的多级屏蔽和电镀工艺包括在印刷线路板基板上布置第一掩模，该第一掩模留下暴露的多个通孔中的一个或多个第一通孔并覆盖剩余的通孔。 第一通孔填充有电阻化合物，从而形成一个或多个第一间隙电阻器。 第一掩模被去除，并且第二掩模设置在印刷线路板基板上，其留下暴露的多个通孔中的一个或多个第二通孔并覆盖剩余的通孔。 第二通孔填充有电阻化合物，从而形成一个或多个第二间隙电阻器。 然后删除第二个面罩。