公开(公告)号：US06807063B2

公开(公告)日：2004-10-19

申请号：US10277485

申请日：2002-10-22

Applicant: Toshihiro Shimura ,  Yoji Ohashi

Inventor： Toshihiro Shimura ,  Yoji Ohashi

IPC: H05K118

CPC classification number: H05K1/0243 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6627 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K3/3442 ,  H05K2201/0715 ,  H05K2201/10727 ,  H05K2201/10969 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high-frequency integrated circuit (IC) module comprising a multilayer mounting board on which an integrated circuit with a plurality of high-frequency signal terminals is mounted, and IC connecting portions disposed on one surface of the multilayer mounting board and respectively connected with the high-frequency signal terminals. The high-frequency IC module further comprises external connection terminal portions disposed at wider intervals than those between the high-frequency signal terminals, high-frequency signal lines provided within the multilayer mounting board, first through holes for connecting the inner ends of the high-frequency signal lines with the IC connecting portions, and second through holes for connecting the outer ends of the high-frequency signal lines with the external connection terminal portions. At least between the high-frequency signal lines, a high-frequency restricting member for ground-connecting both surfaces of the multilayer mounting board and restricting propagation of high-frequency signals is provided along the high-frequency signal lines.

Abstract translation: 一种高频集成电路（IC）模块，包括安装有多个高频信号端子的集成电路的多层安装板，以及设置在所述多层安装板的一个表面上且分别与所述多个安装板连接的IC连接部 高频信号端子。 高频IC模块还包括以比在高频信号端子，高频信号线之间设置的间隔宽的外部连接端子部分，设置在多层安装板内的高频信号线，用于连接高频信号端子的内端的第一通孔， 具有IC连接部的频率信号线，以及用于将高频信号线的外端与外部连接端子部连接的第二通孔。 至少在高频信号线之间，沿着高频信号线提供了用于将多层安装板的两个表面接地连接的高频限制部件和限制高频信号的传播。

公开(公告)号：US20040190294A1

公开(公告)日：2004-09-30

申请号：US10808650

申请日：2004-03-25

Inventor： Jean-Claude Gasquet ,  Alcina Tanghe

IPC: B23K026/22

CPC classification number: F21V29/713 ,  F21S43/14 ,  F21S43/19 ,  F21S45/47 ,  H01L33/64 ,  H05K1/0203 ,  H05K3/301 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3494 ,  H05K2201/0397 ,  H05K2201/10106 ,  H05K2201/10553 ,  H05K2201/10969 ,  H05K2203/107 ,  Y02P70/613 ,  Y10S362/80

Abstract: Method of fixing a power light-emitting diode (1) having a metallic base (2) to a metallic heat-radiating element (3), according to which the base (2) of the light-emitting diode is fixed to the radiating element (3) by laser spot welding (11).

Abstract translation: 将具有金属基体（2）的电力发光二极管（1）固定到金属散热元件（3）的方法，根据该金属基底（2）将发光二极管的基座（2）固定到辐射元件 （3）激光点焊（11）。

公开(公告)号：US06777788B1

公开(公告)日：2004-08-17

申请号：US10241363

申请日：2002-09-10

Applicant: Sharon Ko Mei Wan ,  Jaime A. Bayan

Inventor： Sharon Ko Mei Wan ,  Jaime A. Bayan

IPC: H01L23495

CPC classification number: H05K3/341 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48664 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K2201/09681 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of the invention include an integrated circuit package and methods for its construction. An integrated circuit package of the invention includes a die attach pad and a plurality of lead pads. An integrated circuit die is mounted with the front side of the die attach pad and electrically connected to the plurality of lead pads. Additionally, the backside of the die attach pad includes a pattern of mesas formed thereon. Each of the mesas is configured such that they have a top surface area that is substantially the same size as the surface area of the lead pads. A contact layer of reflowable material is formed on the top surface of the mesas and the lead pads, forming an integrated circuit package with an improved contact layer.

Abstract translation: 本发明的实施例包括集成电路封装及其构造方法。 本发明的集成电路封装包括管芯附接焊盘和多个引线焊盘。 集成电路管芯安装有管芯附接焊盘的前侧并电连接到多个引线焊盘。 此外，管芯附接垫的背面包括形成在其上的台面的图案。 每个台面构造成使得它们具有与引线焊盘的表面积基本上相同的大小的顶表面区域。 在台面和引线焊盘的顶表面上形成可回流材料的接触层，形成具有改进的接触层的集成电路封装。

公开(公告)号：US20040119155A1

公开(公告)日：2004-06-24

申请号：US10729974

申请日：2003-12-09

Inventor： Takeyoshi Hisada ,  Hirofumi Mokuya

IPC: H01L021/44 ,  H01L023/48

CPC classification number: H05K3/202 ,  H01L2924/0002 ,  H05K3/28 ,  H05K3/341 ,  H05K3/3421 ,  H05K2201/0397 ,  H05K2201/10424 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2201/2018 ,  H01L2924/00

Abstract: A metal wiring board includes a metal plate as a substrate. The metal plate is stamped in a predetermined wiring pattern including wiring portions and terminal portions. The metal plate has soldering areas prepared for electrical connection and non-soldering areas coated with solder resist on its surface.

Abstract translation: 金属布线板包括作为基板的金属板。 金属板被冲压成包括布线部分和端子部分的预定布线图案。 金属板具有用于电连接的焊接区域和在其表面上涂覆有阻焊剂的非焊接区域。

公开(公告)号：US20030234441A1

公开(公告)日：2003-12-25

申请号：US10177940

申请日：2002-06-21

Inventor： Charles I. Delheimer

IPC: H01L023/02

CPC classification number: H01L23/498 ,  H01L23/3677 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0206 ,  H05K3/0094 ,  H05K3/341 ,  H05K3/3452 ,  H05K3/42 ,  H05K2201/099 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2203/0455 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and circuit structure for mounting a leadless IC package to a substrate having a thermal pad on a first surface thereof, a plurality of contact pads surrounding the thermal pad, and one or more plated vias in the thermal pad. The leadless package is attached to the substrate with solder that thermally connects the package to the thermal pad. To prevent solder flow into the plated vias during reflow, a solder mask is provided on the first surface of the substrate, at least a portion of which is deposited on the thermal pad and surrounds the plated vias but does not block the plated vias. The solder mask portion defines a barrier between the solder and the plated vias, but allows for outgassing through the vias during solder reflow.

Abstract translation: 一种用于将无铅IC封装安装到其第一表面上具有散热焊盘的衬底，围绕热焊盘的多个接触焊盘以及散热焊盘中的一个或多个镀敷通孔的方法和电路结构。 无引线封装通过将封装热连接到散热焊盘的焊料连接到基板。 为了防止在回流期间焊料流入电镀通孔中，在衬底的第一表面上提供焊料掩模，其中至少一部分沉积在热焊盘上并且围绕电镀通孔，但不阻挡电镀通孔。 焊料掩模部分限定了焊料和镀覆过孔之间的阻挡层，但是允许在回流焊过程中通过通孔而脱气。

公开(公告)号：US20030110622A1

公开(公告)日：2003-06-19

申请号：US10350069

申请日：2003-01-24

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Sachiyuki Nose

IPC: G01R031/26

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/0203 ,  H05K3/341 ,  H05K2201/10734 ,  H05K2201/10969 ,  H05K2203/0235 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014

Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board. The electrode terminal of the semiconductor element is electrically connected to the conductive material of the conductive member exposed to the upper surface of the circuit board via a connecting member.

公开(公告)号：US06333856B1

公开(公告)日：2001-12-25

申请号：US09594485

申请日：2000-06-16

Applicant: Thomas Harju

Inventor： Thomas Harju

IPC: H05K706

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/5385 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/6627 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19032 ,  H01L2924/19107 ,  H05K1/0243 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention relates to an arrangement concerned with multilayer printed circuit boards that enables cavities in said board to be utilized more effectively. A substrate (14) that includes a chip (16) which is connected to the microstrips (17) of the substrate (14) by means of bonding wires (18) is placed on a bonding shelf (13) with the chip (16) orientated towards the bottom of the cavity (6). The microstrips (17) on the substrate (14) therewith come into contact with the microstrips (12) on the bonding shelf (13). The earth plane (15) of the substrate (14) is connected to the upper earth plane (2) by means of bonding wires (19). The arrangement means that the cavity (16) is utilized effectively, at the same time as the substrate (14) protects the underlying chips (7, 16) against mechanical influences.

Abstract translation: 本发明涉及一种有助于更有效地利用所述板中的空​​腔的多层印刷电路板的布置。 包括通过接合线（18）与衬底（14）的微带（17）连接的芯片（16）的衬底（14）被放置在具有芯片（16）的接合架（13）上， 朝向空腔（6）的底部。 衬底（14）上的微带（17）与粘结搁板（13）上的微带（12）接触。 衬底（14）的接地平面（15）通过接合线（19）连接到上接地平面（2）。 该装置意味着空腔（16）被有效利用，同时衬底（14）保护下面的芯片（7,16）免受机械影响。

公开(公告)号：US20010041370A1

公开(公告)日：2001-11-15

申请号：US09430559

申请日：1999-10-29

Inventor： MIKE BROOKS ,  WALTER L. MODEN

IPC: H01L021/00

CPC classification number: H01L23/36 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H05K3/341 ,  H05K2201/10689 ,  H05K2201/1078 ,  H05K2201/1084 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

Abstract translation: 提供一种用于制造封装的半导体封装和方法。 封装包括半导体管芯和与管芯热连通的散热器。 散热器包括适于形成接合连接的一个或多个焊盘结构，以及衬底上的触点的热路径。 该方法包括在类似于引线框架的框架上形成多个散热器，以及蚀刻或冲压散热器上的焊盘结构。 然后可以将该框架连接到包含封装的骰子的引线框架上，并且该组件被单个化以形成单独的封装。 这些封装可用于形成诸如电路板组件和多芯片模块之类的电子组件。

公开(公告)号：US06238953B1

公开(公告)日：2001-05-29

申请号：US09480257

申请日：2000-01-11

Applicant: Kenzo Tanaka ,  Takahiro Yotsumoto

Inventor： Kenzo Tanaka ,  Takahiro Yotsumoto

IPC: H01L2144

CPC classification number: H05K3/341 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Fabrication of a semiconductor device, with an improved level of exposure of the rear surface of a die pad is enabled during the fabrication of which deformation of a die pad in a resin-encapsulating step is prevented from occurring, and which can be mounted on a printed wiring board with a sufficient soldering strength. In a resin-encapsulated semiconductor device in which a semiconductor element is placed on the front surface of a die pad of a lead frame including: the die pad; and support bars of the die pad that protrude outwardly from sides of the die pad, the semiconductor element and its periphery are encapsulated with a resin material while the rear surface of the die pad is exposed to the external environment, a groove is formed on the rear surface of the support bar so that the groove traverses the support bar in the neighborhood of the boundary between the support bar and the die pad along a direction intersecting a protruding direction of the support bar. The groove may be formed on the front surface of a support bar.

Abstract translation: 在制造期间，能够防止在树脂密封步骤中的芯片焊盘的变形发生，并且可以安装在模具衬垫的后表面上的半导体器件的制造中，其具有改善的裸片焊盘的后表面的曝光水平 印刷电路板具有足够的焊接强度。 在其中将半导体元件放置在引线框架的管芯焊盘的前表面上的树脂封装的半导体器件中，包括：管芯焊盘; 以及从芯片焊盘的侧面向外突出的芯片焊盘的支撑杆，半导体元件及其周边用树脂材料封装，同时芯片焊盘的后表面暴露于外部环境， 支撑杆的后表面，使得槽沿着与支撑杆的突出方向相交的方向在支撑杆和模具垫之间的边界附近横过支撑杆。 凹槽可以形成在支撑杆的前表面上。

公开(公告)号：US20010000915A1

公开(公告)日：2001-05-10

申请号：US09749422

申请日：2000-12-28

Inventor： Roman Katchmar

IPC: H01L021/447

CPC classification number: H01L23/49838 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/094 ,  H05K2201/10969 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A surface mount area-array integrated circuit package is disclosed. The package consists of a package substrate having conductive vias and internal and external conductive traces, a semiconductor die electrically and mechanically connected to the top surface of package substrate, an area-array of conductive surface mount terminations electrically and mechanically connected to the bottom of the package substrate, and at least one adhesive mass. The at least one adhesive mass is located on the bottom of the package substrate and replaces the conductive terminations in the area(s) where the joint strain energy density is calculated to be the greatest. When mounted on a substrate, the at least one adhesive mass adheres the package to the substrate. Increased mechanical and electrical reliability is thus achieved.