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    SEMICONDUCTOR DEVICE AND WIRING PART THEREOF
    71.
    发明申请
    SEMICONDUCTOR DEVICE AND WIRING PART THEREOF 有权
    半导体器件及其接线部分

    公开(公告)号：US20080266031A1

    公开(公告)日：2008-10-30

    申请号：US12060941

    申请日：2008-04-02

    Applicant: Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

    Inventor： Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

    IPC: H01P1/00

    CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/111 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10734 ,  H01L2924/00

    Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.

    Abstract translation: 提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。 安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。 去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。 接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。 第一金属电极板和第二金属电极板在其间插入厚度等于或小于1μm的电介质膜。

    Semiconductor device
    72.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07187069B2

    公开(公告)日：2007-03-06

    申请号：US10981676

    申请日：2004-11-05

    Applicant: Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

    Inventor： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

    IPC: H01L23/02 ,  H01L23/34

    CPC classification number: H01L23/642 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/647 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/3011

    Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

    Abstract translation: 本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线 并引入输出缓冲区。 更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离 方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

    Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
    74.
    发明授权
    Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM 有权
    半导体存储器模块，存储器系统，电路，半导体器件和DIMM

    公开(公告)号：US07095661B2

    公开(公告)日：2006-08-22

    申请号：US11019274

    申请日：2004-12-23

    Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

    Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

    IPC: G11C99/00

    CPC classification number: G11C29/028 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50012

    Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.

    Abstract translation: 存在的问题是，由于DIMM中的C / A信号通过DIMM中的寄存器分配到相应的DRAM，DQ信号直接从DIMM中的端子连接，因此它们的时序难以同步。 提供用于加速高速运行的DIMM的C / A信号的寄存器，寄存器的布线设置为菊花链布线。 然后，通过设置在DRAM中的定时调整电路，根据DRAM的位置而不同的C / A信号和时钟信号之间的布线延迟时间差使得从寄存器的延迟时间之和 并且由于定时调整电路引起的延迟量等于最远的DRAM的延迟时间。

    Equal-amplitude signaling directional coupling bus
    76.
    发明申请
    Equal-amplitude signaling directional coupling bus 失效
    等幅信号定向耦合总线

    公开(公告)号：US20050251598A1

    公开(公告)日：2005-11-10

    申请号：US10517591

    申请日：2003-07-01

    Applicant: Hideki Osaka

    Inventor： Hideki Osaka

    IPC: G06F13/40 ,  G06F13/00

    CPC classification number: G06F13/4086

    Abstract: In ultrahigh speed data transfer, a drive pulse is attenuated due to a skin effect and a dielectric loss, and a tail generated by a sub coupler extends as the drive pulse propagates on the main line. For that reason, an intersymbol interference becomes large, which causes jitters. In a memory system to which a plurality of DRAM memory modules are connected, in order to transfer data at high-speed, directional couplers are wired between a main controller and each of the modules, and the coupling lengths become longer with farther ends, thereby suppressing jitters. The directional couplers are wired between the main controller and each of the modules, and the coupling lengths are made longer with the farther ends with the results that the generated signal amounts are made constant, and jitters of the wiring and receiver delay are suppressed.

    Abstract translation: 在超高速数据传输中，驱动脉冲由于皮肤效应和介电损耗而衰减，并且由辅助耦合器产生的尾部随着驱动脉冲在主线上传播而延长。 因此，码间干扰变大，导致抖动。 在连接有多个DRAM存储器模块的存储器系统中，为了在高速下传输数据，定向耦合器布线在主控制器和每个模块之间，并且耦合长度随着更远的端部变长，从而 抑制不安 定向耦合器连接在主控制器和每个模块之间，并且耦合长度随着更远的端部变长而产生的信号量变得恒定，并且抑制了布线和接收器延迟的抖动。

    Gap-coupling bus system
    78.
    发明授权
    Gap-coupling bus system 有权
    间隙耦合总线系统

    公开(公告)号：US06600790B1

    公开(公告)日：2003-07-29

    申请号：US09297359

    申请日：1999-04-30

    Applicant: Masaya Umemura ,  Hideki Osaka

    Inventor： Masaya Umemura ,  Hideki Osaka

    IPC: H04B300

    CPC classification number: G06F13/4072 ,  H05K1/0228 ,  H05K1/023 ,  H05K1/0245 ,  H05K2201/09263 ,  H05K2201/097 ,  H05K2201/10022

    Abstract: There is provided a gap coupling type bus system, which makes it possible to mutually transfer data between all the modules connected to the bus. The gap coupling type bus system comprises for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines (21-26) respectively connected to the at least three modules (11-16); and terminating resistors (31-36) connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line. Those at least three signal lines (21-26) have portions (1-2, 1-3, 2-3, . . . ) laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of those at least three modules (11-16).

    Abstract translation: 提供了一种间隙耦合型总线系统，这使得可以在连接到总线的所有模块之间相互传送数据。 间隙耦合型总线系统包括至少三个模块，每个模块设置有至少一个用于发送和接收信号的发送/接收电路：至少三个信号线（21-26），分别连接到至少三个模块 （11-16）; 以及连接到信号线的另一端的相应信号线的端接电阻器（31-36），每个终端电阻器具有与信号线的特征阻抗大致相同的值。 那些至少三条信号线（21-26）具有以预定间隙彼此平行放置的部分（1-2,1-3,3-3 ...），对应于不同的两个模块的每个组合 至少有三个模块（11-16）。

    Source-clock-synchronized memory system and memory unit
    79.
    发明授权
    Source-clock-synchronized memory system and memory unit 失效
    源时钟同步存储器系统和存储单元

    公开(公告)号：US06034878A

    公开(公告)日：2000-03-07

    申请号：US992210

    申请日：1997-12-16

    Applicant: Hideki Osaka ,  Masaya Umemura ,  Akira Yamagiwa ,  Toshitsugu Takekuma

    Inventor： Hideki Osaka ,  Masaya Umemura ,  Akira Yamagiwa ,  Toshitsugu Takekuma

    IPC: G06F12/06 ,  G06F1/10 ,  G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C11/401 ,  G11C11/407 ,  G11C13/00

    CPC classification number: G06F13/1684

    Abstract: A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

    Abstract translation: 源时钟同步的存储器系统，每个存储体具有大的数据存储容量和高的安装密度。 本发明包括具有通过第一连接器C1安装在基板上的第一存储器提升板B1和通过第二连接器C2安装在基板BB上的第二存储器提升板B2的存储单元。 第一存储器提升板具有安装在其前表面上的多个第一存储器模块，并且第二存储器提升板具有安装在其前表面上的多个第二存储器模块。 第一和第二存储器提升板被布置成使得第一存储器提升板的后表面面向第二存储器提升板的后表面。 本发明还包括板连接连接器，用于将第一存储器提升板上的信号线连接到第二存储器提升板上的相应信号线。

    Data transfer system, computer system and active-line inserted/withdrawn functional circuit board
    80.
    发明授权
    Data transfer system, computer system and active-line inserted/withdrawn functional circuit board 失效
    数据传输系统，计算机系统和有源线插拔功能电路板

    公开(公告)号：US5787261A

    公开(公告)日：1998-07-28

    申请号：US563106

    申请日：1995-11-27

    Applicant: Hideki Osaka ,  Akira Yamagiwa ,  Ryoichi Kurihara ,  Masao Inoue

    Inventor： Hideki Osaka ,  Akira Yamagiwa ,  Ryoichi Kurihara ,  Masao Inoue

    IPC: G06F13/40 ,  G06F13/00

    CPC classification number: G06F13/4081

    Abstract: It is an object of the present invention to provide an active-line inserted/withdrawn functional circuit board, a data transfer system and a computer system which systems allow the functional circuit board to be inserted and withdrawn with signal lines remaining in an active state while achieving a high speed data-transfer of a bus, and the reliability to be enhanced by eliminating malfunctions which occur particularly during the insertion of a functional circuit board. The data transfer system or the computer system comprising: a functional circuit board having a functional circuit, a pre-charge resistor and a switching element connected in parallel to an input/output signal path of the functional circuit and a switching control means for controlling the conduction of the switching element through synchronization with a delayed clock signal resulting from delaying a bus clock signal for use in data transfers through the bus by a time shorter than a bus-clock cycle time of the bus clock signal; and a connector provided on an input/output end of the parallel connection of the pre-charge resistor and the switching element, whereby the functional circuit board can be inserted and withdrawn to and from the bus.

    Abstract translation: 本发明的目的是提供一种有源线插入/取出功能电路板，数据传输系统和计算机系统，其中系统允许功能电路板被插入和撤回，信号线保持在活动状态，同时 实现总线的高速数据传送，以及通过消除特别是在插入功能电路板期间发生的故障而增强的可靠性。 数据传送系统或计算机系统包括：功能电路板，具有与功能电路的输入/输出信号路径并联连接的功能电路，预充电电阻和开关元件;以及开关控制装置，用于控制功能电路 开关元件通过与延迟总线时钟信号的延迟时钟信号同步地传导，以用于通过总线的数据传输比总线时钟信号的总线时钟周期时间短的时间; 以及设置在预充电电阻器和开关元件的并联连接的输入/输出端上的连接器，由此功能电路板可以从总线插入和拔出。

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