公开(公告)号：US09019770B2

公开(公告)日：2015-04-28

申请号：US13901571

申请日：2013-05-24

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括将测试电压施加到可重写非易失性存储器模块的字线以读取多个验证位数据。 该方法还包括计算在验证位数据中识别为第一状态的位数据的变化，获得基于该变化设置的新的读取电压值，并且用新的读取电压值集更新用于字线的阈值电压 。 该方法还包括使用更新的阈值电压来从连接到字线的存储器单元形成的物理页读取数据。 因此，可以正确地识别可重写非易失性存储器模块中的存储单元的存储状态，从而防止存储在存储单元中的数据丢失。

公开(公告)号：US20150067446A1

公开(公告)日：2015-03-05

申请号：US14054848

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shao-Wei Yen ,  Yu-Hsiang Lin ,  Wei Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: H03M13/11 ,  G06F11/10

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6577

Abstract: A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased.

Abstract translation: 提供了解码方法，存储器存储装置和可重写非易失性存储器模块。 该方法包括：根据读取电压从可重写非易失性存储器模块读取多个位; 对比特执行低密度奇偶校验（LDPC）算法的奇偶校验以获得校正子，并且每个比特对应于至少一个综合征; 确定所述位是否具有根据所述综合征的错误; 如果这些比特具有错误，则根据与每个比特对应的校验子获得每个比特的综合征权重; 根据每个位的校正子权重获得每个比特的初始值; 以及根据初始值对该比特执行LDPC算法的第一迭代解码。 因此，解码速度增加。

公开(公告)号：US08972653B2

公开(公告)日：2015-03-03

申请号：US13749697

申请日：2013-01-25

Applicant: Phison Electronics Corp.

Inventor： Wei Lin

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F2212/7211

Abstract: A memory management method and a memory controller and a memory storage apparatus using the same are provided. The method includes applying different detection biases to read data stored in physical pages of a rewritable non-volatile memory module and calculating the number of error bits according the read data. The method further includes estimating a value of a wearing degree of each physical page according to the calculated number of error bits and operating the rewritable non-volatile memory module according to the value of the wearing degree of each physical page. Accordingly, the method can effectively identify the wearing degree of the rewritable non-volatile memory module and operate the rewritable non-volatile memory module by applying a corresponding management mechanism, so as to prevent data errors.

Abstract translation: 提供了存储器管理方法和存储器控制器以及使用其的存储器存储装置。 该方法包括应用不同的检测偏差来读取存储在可重写非易失性存储器模块的物理页面中的数据，并根据读取的数据计算错误位数。 该方法还包括根据计算出的错误比特数来估计每个物理页面的磨损程度的值，并根据每个物理页面的磨损程度的值操作可重写非易失性存储器模块。 因此，该方法可以有效地识别可重写非易失性存储器模块的磨损程度并通过应用相应的管理机制来操作可重写非易失性存储器模块，从而防止数据错误。

公开(公告)号：US20150006983A1

公开(公告)日：2015-01-01

申请号：US14018436

申请日：2013-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam ,  Tzung-Lin Wu ,  Kuo-Yi Cheng

IPC: G11C29/50 ,  G11C16/26

CPC classification number: G11C29/50004 ,  G11C16/00 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的读取电压设置方法。 该方法包括：读取存储在字线的存储单元中的测试数据，以获得相应的临界电压分布，并基于相应的临界电压分布识别与字线对应的默认读取电压; 将根据所述默认读取电压获得的多个测试读取电压施加到所述字线以读取多个测试页面数据; 以及根据所述测试页数据的多个错误位数中的最小误差位数确定与所述字线对应的优化读取电压。 该方法还包括计算默认读取电压和优化读取电压之间的差值作为对应于字线的读取电压调整值，并将读取电压调整值记录在重试表中。

公开(公告)号：US20140286105A1

公开(公告)日：2014-09-25

申请号：US13917621

申请日：2013-06-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/26 ,  H01L29/792

CPC classification number: G11C16/14 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/7926

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract translation: 提供NAND闪存单元，操作方法和读取方法。 NAND闪存单元包括多个栅极层，隧道层，电荷俘获层，导体层和第二介电层。 在栅极层之间的两个相邻栅极层之间包括第一介电层。 隧道层，电荷俘获层，导体层和第二介电层穿透栅极层。 电荷捕获层设置在隧道层和栅极层之间，第二介电层设置在导体层和隧道层之间。 因此，可以增加擦除速度; 电荷捕获层可以被修复; 可以提高栅极层的可控性。

公开(公告)号：US20140050024A1

公开(公告)日：2014-02-20

申请号：US13781718

申请日：2013-02-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Riichiro Shirota ,  Wei Lin

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483

Abstract: A data reading method for a rewritable non-volatile memory module, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes applying a bias for reading data to a target word line electrically connected to a target memory cell and applying a bias for selecting bit lines to a target bit line electrically connected to the target memory cell. The method also includes applying a first bias to at least one word line adjacent to the target word line and applying a second bias to other word lines, and the first bias is lower than the second bias. The method further includes outputting a corresponding value according to a conduction state of a channel of the target memory cell. Accordingly, the method can effectively increase the gate controllability of the memory cell to prevent read errors.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据读取方法，使用该方法的存储器控​​制器和使用该方法的存储器存储装置。 所述方法包括：向与目标存储单元电连接的目标字线上应用读取数据的偏置，并向与目标存储单元电连接的目标位线施加用于选择位线的偏置。 该方法还包括将第一偏压施加到与目标字线相邻的至少一个字线，并将第二偏压施加到其它字线，并且第一偏压低于第二偏压。 该方法还包括根据目标存储器单元的通道的导通状态输出相应的值。 因此，该方法可以有效地提高存储单元的门控制性，以防止读错误。

公开(公告)号：US12148486B2

公开(公告)日：2024-11-19

申请号：US18181546

申请日：2023-03-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiao-Yi Lin ,  Shih-Jia Zeng ,  Chen Yang Tang ,  Shi-Chieh Hsu ,  Wei Lin

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: A read voltage adjustment method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a write command sequence instructing to program a plurality of first memory cells in a rewritable non-volatile memory module; sending a first read command sequence instructing to read the programmed first memory cells using a first read voltage level to obtain first count information; obtaining first compensation information corresponding to the first read voltage level, wherein the first compensation information reflects a deviation in evenly programming the first memory cells to a plurality of states; and adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.

公开(公告)号：US12124743B2

公开(公告)日：2024-10-22

申请号：US18077190

申请日：2022-12-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Heng Liu ,  Yu-Siang Yang ,  An-Cheng Liu ,  Wei Lin

IPC: G11C16/34 ,  G06F3/06

CPC classification number: G06F3/0679 ,  G11C16/3422

Abstract: A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.

公开(公告)号：US20240304235A1

公开(公告)日：2024-09-12

申请号：US18301275

申请日：2023-04-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Hao Chen ,  Po-Cheng Su ,  Shih-Jia Zeng ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C11/409 ,  G06F3/0679 ,  G11C16/26

Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.

公开(公告)号：US20240201857A1

公开(公告)日：2024-06-20

申请号：US18168573

申请日：2023-02-14

Applicant: Phison Electronics Corp.

Inventor： Po-Cheng Su ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.