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    Inverted CSP Stacking System and Method
    72.
    发明申请
    Inverted CSP Stacking System and Method 审中-公开
    倒置CSP堆叠系统和方法

    公开(公告)号：US20080079132A1

    公开(公告)日：2008-04-03

    申请号：US11926494

    申请日：2007-10-29

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H01L23/02 ,  H01L21/02

    CPC classification number: H05K1/147 ,  H01L23/5387 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/10734

    Abstract: Two or more integrated circuits are stacked into a high density circuit module. The lower IC is inverted. Electrical connection to the integrated circuits is made by module contacts on a flexible circuit extending along the lower portion of the module. In one embodiment, the flexible circuit provides a balanced electrical connection to two CSP integrated circuits. In another embodiment, the flexible circuit provides a balanced electrical connection to inter-flex contacts of additional flexible circuits on two submodules. The additional flexible circuits provide further balanced connections to CSP integrated circuits in each submodule.

    Abstract translation: 两个或多个集成电路堆叠成高密度电路模块。 下部IC倒置。 与集成电路的电连接由沿着模块的下部延伸的柔性电路上的模块触点进行。 在一个实施例中，柔性电路提供与两个CSP集成电路的平衡电连接。 在另一个实施例中，柔性电路提供与两个子模块上的附加柔性电路的相互柔性触点的平衡电连接。 额外的灵活电路提供了进一步平衡的连接到每个子模块中的CSP集成电路。

    High Capacity Thin Module System and Method
    73.
    发明申请
    High Capacity Thin Module System and Method 有权
    高容量薄模块系统和方法

    公开(公告)号：US20080030972A1

    公开(公告)日：2008-02-07

    申请号：US11869687

    申请日：2007-10-09

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H05K1/11

    CPC classification number: G11C5/04 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

    Abstract: Multiple DIMM circuits or ins tantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

    Abstract translation: 多个DIMM电路或插图在单个模块中呈现。 在一些实施例中，存储器集成电路（优选CSP）和伴随的AMB或伴随的存储器寄存器被布置在柔性电路的每一侧的两个场中的两个等级中。 柔性电路具有沿着一侧设置的扩展触点。 柔性电路围绕支撑衬底或板设置，以在构造的模块的每一侧上放置一个完整的DIMM电路或实例化。 在替代但也是优选实施例中，最靠近基板的柔性电路侧的IC至少部分地设置在优选实施例中在基板中的窗口，凹部或切口区域中。 其他实施例可以仅填充柔性电路的一侧，或者可以仅移除足够的衬底材料以减少但不消除整个衬底对整体轮廓的贡献。 柔性电路可以表现出一个或两个或更多个导电层，并且可以具有分层结构的变化或具有分裂层。 其他实施例可能错开或偏移IC或包括更多数量的IC。

    Inverted CSP stacking system and method
    74.
    发明授权
    Inverted CSP stacking system and method 有权
    倒置CSP堆垛系统及方法

    公开(公告)号：US07309914B2

    公开(公告)日：2007-12-18

    申请号：US11039615

    申请日：2005-01-20

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52

    CPC classification number: H05K1/147 ,  H01L23/5387 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/10734

    Abstract: Two or more integrated circuits are stacked into a high density circuit module. The lower IC is inverted. Electrical connection to the integrated circuits is made by module contacts on a flexible circuit extending along the lower portion of the module. In one embodiment, the flexible circuit provides a balanced electrical connection to two CSP integrated circuits. In another embodiment, the flexible circuit provides a balanced electrical connection to inter-flex contacts of additional flexible circuits on two submodules. The additional flexible circuits provide further balanced connections to CSP integrated circuits in each submodule.

    Abstract translation: 两个或多个集成电路堆叠成高密度电路模块。 下部IC倒置。 与集成电路的电连接由沿着模块的下部延伸的柔性电路上的模块触点进行。 在一个实施例中，柔性电路提供与两个CSP集成电路的平衡电连接。 在另一个实施例中，柔性电路提供与两个子模块上的附加柔性电路的相互柔性触点的平衡电连接。 额外的灵活电路提供了进一步平衡的连接到每个子模块中的CSP集成电路。

    POLARIZED PHASE MICROSCOPY
    77.
    发明申请
    POLARIZED PHASE MICROSCOPY 审中-公开
    极化相显微镜

    公开(公告)号：US20070091427A1

    公开(公告)日：2007-04-26

    申请号：US11552953

    申请日：2006-10-25

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: G02B21/06

    CPC classification number: G02B21/0092 ,  G02B21/14 ,  G02B21/16 ,  G02B27/52

    Abstract: A system and method of generating and acquiring phase contrast microscope images while minimizing interference with the intensity and optical quality of other microscopy modalities employing polarization and attenuation strategies for phase microscopy applications. A plane polarizing objective phase ring may be used in conjunction with a phase microscopy apparatus. Attenuated light may be controlled such that transparency may be selectively provided with respect to light in a predetermined plane. Illumination outside of the predetermined plane may be selected for phase microscopy applications. Accordingly, a polarizing objective phase ring effective for enabling polarized phase microscopy may reduce interfere with normal usage of the microscope for other applications such as, for example, fluorescence microscopy.

    Abstract translation: 一种生成和获取相位显微镜图像的系统和方法，同时最小化使用相位显微镜应用的极化和衰减策略的其他显微镜模式的强度和光学质量的干扰。 平面偏振目标相位环可以与相位显微镜装置结合使用。 可以控制衰减的光，使得可以相对于预定平面中的光选择性地提供透明度。 对于相位显微镜应用，可以选择预定平面外的照明。 因此，对于允许极化相位显微镜有效的偏振目标相位环可以减少对于其它应用例如荧光显微镜的显微镜的正常使用的干扰。

    Purification process
    78.
    发明申请
    Purification process 审中-公开
    净化过程

    公开(公告)号：US20060130610A1

    公开(公告)日：2006-06-22

    申请号：US10529234

    申请日：2003-09-24

    Applicant: Charles Ward-Close ,  Alastair Godfrey ,  Paul Goodwin

    Inventor： Charles Ward-Close ,  Alastair Godfrey ,  Paul Goodwin

    IPC: B22F9/04

    CPC classification number: C22B34/1295 ,  C22B9/14 ,  C22B34/129

    Abstract: A method for purifying metal M1 particles manufactured by an electrochemical reduction process, the method comprising the steps of introducing the metal M1 particles into a heat source (13) at a temperature substantially equal to or higher than the melting point of M1 so as to cause vaporisation of some or substantially all of the contaminating impurities present, removing the vaporised Impurities from the vicinity of the particles, and cooling the purified metal M1 particles. The purified particles can be used directly in lower temperature powder metallurgy processes and have fully dense spherical particle morphology, imparting good flowability. The purification process can also be incorporated as an integral stage of sheet or stock production processes based on particle feedstock's that have been produced by electrochemical reduction.

    Abstract translation: 一种用于净化由电化学还原法制备的金属M 1 O 2颗粒的方法，所述方法包括以下步骤：将金属M 1 N 2颗粒引入热源（13）中， 温度基本上等于或高于M 1 C的熔点，以便使部分或基本上所有的污染杂质蒸发，从颗粒附近除去蒸发的杂质，并冷却 纯化的金属M 1 N 2颗粒。 纯化的颗粒可以直接用于较低温度的粉末冶金工艺，并具有完全致密的球形颗粒形态，赋予良好的流动性。 净化过程也可以作为基于通过电化学还原生产的颗粒原料的片材或原料生产方法的整体阶段。

    Circuit module with thermal casing systems and methods
    79.
    发明申请
    Circuit module with thermal casing systems and methods 有权
    具有热套管系统和方法的电路模块

    公开(公告)号：US20060090102A1

    公开(公告)日：2006-04-27

    申请号：US11283355

    申请日：2005-11-18

    Applicant: James Wehrly ,  James Wilder ,  Mark Wolfe ,  Paul Goodwin

    Inventor： James Wehrly ,  James Wilder ,  Mark Wolfe ,  Paul Goodwin

    IPC: G06F11/00

    CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

    Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. The populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally-conductive materials and one or more thermal spreaders are disposed in thermal contact with at least some of the constituent integrated circuitry of the module. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to, higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

    Abstract translation: 灵活的电路装有沿主要侧面或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧上，在衬底的一侧或两侧上具有一层或多层集成电路。 衬底形式优选地由导热材料设计，并且一个或多个热扩散器设置成与模块的组成集成电路中的至少一些热接触。 可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。 在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的放大表面。

    Compact module system and method
    80.
    发明申请
    Compact module system and method 有权

    公开(公告)号：US20060050592A1

    公开(公告)日：2006-03-09

    申请号：US11187269

    申请日：2005-07-22

    Applicant: James Cady ,  James Wehrly ,  Paul Goodwin

    Inventor： James Cady ,  James Wehrly ,  Paul Goodwin

    IPC: G11C8/00

    CPC classification number: H05K1/189 ,  H05K2201/056 ,  H05K2201/10159 ,  H05K2201/10189

    Abstract: A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.

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