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    REDUCTION OF CHIPPING DAMAGE TO MEMS STRUCTURE
    71.
    发明申请
    REDUCTION OF CHIPPING DAMAGE TO MEMS STRUCTURE 有权
    减少对MEMS结构的损伤

    公开(公告)号：US20150076631A1

    公开(公告)日：2015-03-19

    申请号：US14225275

    申请日：2014-03-25

    Applicant: InvenSense, Inc.

    Inventor： Jongwoo SHIN ,  Kirt Reed WILLIAMS ,  Cerina ZHANG ,  Kuolung (Dino) LEI

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81C1/00103 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133

    Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.

    Abstract translation: MEMS（微机电系统）结构包括MEMS晶片。 MEMS晶片包括具有通过布置在盖和结构层之间的电介质层结合到结构层的空腔的盖。 阐述了MEMS器件的独特结构和提供这些器件的方法，其部分地通过使用多步骤深反应离子蚀刻（DRIE）形成蚀刻掩模光致抗蚀剂回流来形成圆形，扇形或倒角的MEMS轮廓， 不同的蚀刻特性，或通过DRIE后的蚀刻。

    Methods and Apparatus for MEMS Devices with Increased Sensitivity
    72.
    发明申请
    Methods and Apparatus for MEMS Devices with Increased Sensitivity 有权
    具有增加灵敏度的MEMS器件的方法和装置

    公开(公告)号：US20140252358A1

    公开(公告)日：2014-09-11

    申请号：US13790617

    申请日：2013-03-08

    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

    Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/0059 ,  B81B3/0056 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C1/00158 ,  B81C1/00714 ,  B81C2201/0112 ,  B81C2201/0132 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125

    Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.

    Abstract translation: 用于形成MEMS器件的方法和装置。 一种装置包括具有第一厚度的半导体衬底的至少一部分并被图案化以形成可移动质量块; 形成第一电容的第一板的移动感测电极; 所述至少一个锚定体从所述半导体衬底图案化并且具有形成所述第一电容的所述第二板的部分并与所述第一板间隔开第一间隙; 图案化的第二厚度的半导体材料层，以形成形成第二电容的第一板的第一电极，并进一步图案化以形成覆盖至少一个锚的第二电极，并形成间隔第二间隙的第二板，该第二间隔较小 比第一个差距; 其中形成的总电容是第一电容和第二电容之和。 公开了方法。

    METHOD FOR PRODUCING TRENCH-LIKE DEPRESSIONS IN THE SURFACE OF A WAFER
    73.
    发明申请
    METHOD FOR PRODUCING TRENCH-LIKE DEPRESSIONS IN THE SURFACE OF A WAFER 有权
    用于在波浪表面产生类似沉积物的方法

    公开(公告)号：US20130263847A1

    公开(公告)日：2013-10-10

    申请号：US13856637

    申请日：2013-04-04

    Applicant: Klaus KADEL

    Inventor： Klaus KADEL

    IPC: A61M11/02

    CPC classification number: A61M11/02 ,  B81C1/00206 ,  B81C2201/0112 ,  B81C2201/018

    Abstract: In a method of producing trench-like depressions (24) in the surface of a wafer (27), particularly a silicon wafer, by plasma etching, in which the depressions (24) are produced by alternate passivation and etching, each depression (24) in its final geometry is provided with a protective layer (30) of the polytetrafluoroethylene type.

    Abstract translation: 在通过等离子体蚀刻在晶片（27）表面（特别是硅晶片）的表面中制造沟槽状凹陷（24）的方法中，通过交替的钝化和蚀刻产生凹陷（24），每个凹陷（24 ）在其最终几何形状中设置有聚四氟乙烯类型的保护层（30）。

    Method and apparatus for etching
    74.
    发明授权
    Method and apparatus for etching 失效
    蚀刻方法和设备

    公开(公告)号：US08298959B2

    公开(公告)日：2012-10-30

    申请号：US12786006

    申请日：2010-05-24

    Applicant: Alan Cheshire

    Inventor： Alan Cheshire

    IPC: H01L21/302

    CPC classification number: B81C1/00531 ,  B81C2201/0112 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32449 ,  H01L21/30655

    Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that includes a) depositing a polymer on a substrate in an etch reactor, b) etching the substrate using a gas mixture including a fluorine-containing gas and oxygen in the etch reactor, c) etching a silicon-containing layer the substrate using a fluorine-containing gas without mixing oxygen in the etch reactor, and d) repeating a), b) and c) until an endpoint of a feature etched into the silicon-containing layer is reached.

    Abstract translation: 本发明的实施例涉及一种基板蚀刻方法和装置。 在一个实施例中，提供了一种在等离子体蚀刻反应器中蚀刻衬底的方法，其包括：a）在蚀刻反应器中在衬底上沉积聚合物，b）使用包含含氟气体和氧的气体混合物蚀刻衬底 蚀刻反应器，c）使用含氟气体在含氧气体中蚀刻含硅层，而不在蚀刻反应器中混合氧，以及d）重复a），b）和c）直到蚀刻到硅中的特征的端点 到达层。

    Method of forming and patterning conformal insulation layer in vias and etched structures
    75.
    发明申请
    Method of forming and patterning conformal insulation layer in vias and etched structures 审中-公开
    在通孔和蚀刻结构中形成和构图保形绝缘层的方法

    公开(公告)号：US20110207323A1

    公开(公告)日：2011-08-25

    申请号：US12712339

    申请日：2010-02-25

    Applicant: Robert Ditizio

    Inventor： Robert Ditizio

    IPC: H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76898 ,  B81B2207/07 ,  B81C1/00087 ,  B81C2201/0112 ,  H01L21/02118 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/3065 ,  H01L21/30655

    Abstract: Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.

    Abstract translation: 使用在掩模层下方形成底切轮廓的蚀刻工艺在衬底中形成通孔。 通孔用保形绝缘层涂覆，并且将蚀刻工艺施加到结构以从绝缘层移除绝缘层，同时将绝缘层留在通孔的垂直侧壁上。 通过底切硬掩模在回蚀过程中保护通孔的顶部区域。

    Method of through-etching substrate
    80.
    发明授权
    Method of through-etching substrate 失效
    通过蚀刻基板的方法

    公开(公告)号：US06821901B2

    公开(公告)日：2004-11-23

    申请号：US10084622

    申请日：2002-02-28

    Applicant: Seung-jin Song ,  Kyoungdoug Min ,  Young-chang Joo ,  Hong-seok Min ,  Sejun Kim ,  Kun-joong Park

    Inventor： Seung-jin Song ,  Kyoungdoug Min ,  Young-chang Joo ,  Hong-seok Min ,  Sejun Kim ,  Kun-joong Park

    IPC: H01L21311

    CPC classification number: B81C1/00087 ,  B81C2201/0107 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/3081 ,  H01L21/32134

    Abstract: A method of through-etching a substrate that is simplified and by which the flow of ions can be kept to be regular during a plasma dry etching process, is provided. According to this method, a buffer layer is formed on a first plane of the substrate, a metal layer is formed on the buffer layer, an etching mask pattern is formed on a second plane opposite to the first plane, and the substrate is through-etched with the etching mask pattern as an etching mask. Preferably, the substrate is formed of a single-crystal silicon, the buffer layer is formed of silicon dioxide, and the metal layer is formed of aluminum.

    Abstract translation: 提供了一种通过蚀刻简化的衬底的方法，并且通过该方法可以在等离子体干蚀刻工艺期间将离子流保持为规则的方法。 根据该方法，在基板的第一平面上形成缓冲层，在缓冲层上形成金属层，在与第一平面相反的第二平面上形成蚀刻掩模图案， 用蚀刻掩模图案蚀刻作为蚀刻掩模。 优选地，基板由单晶硅形成，缓冲层由二氧化硅形成，金属层由铝形成。

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