公开(公告)号：US20190090360A1

公开(公告)日：2019-03-21

申请号：US15940988

申请日：2018-03-30

Applicant: AZOTEK CO., LTD.

Inventor： Hung-Jung LEE

IPC: H05K3/46 ,  H05K3/06 ,  H05K3/40 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K3/4644 ,  H05K1/024 ,  H05K1/032 ,  H05K1/113 ,  H05K3/061 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/0145 ,  H05K2201/0341 ,  H05K2203/025 ,  H05K2203/0759 ,  H05K2203/0783

Abstract: A manufacturing method of a composite substrate is provided. A first conductive layer is formed on a first liquid crystal polymer layer. The first conductive layer is patterned to form a patterned first conductive layer. A second liquid crystal polymer layer including a soluble liquid crystal polymer is formed to cover the patterned first conductive layer. The second liquid crystal polymer layer which is on the patterned first conductive layer is removed.

公开(公告)号：US09769933B2

公开(公告)日：2017-09-19

申请号：US14514819

申请日：2014-10-15

Applicant: Hitachi Metals, Ltd.

Inventor： Hideyuki Sagawa ,  Keisuke Fujito ,  Takayuki Tsuji ,  Kotaro Tanaka ,  Hiromitsu Kuroda

IPC: H05K1/09 ,  H05K3/10 ,  H05K3/28 ,  H05K3/06 ,  H05K3/24

CPC classification number: H05K3/282 ,  H05K3/06 ,  H05K3/244 ,  H05K2201/0341 ,  H05K2201/0355 ,  H05K2203/0315 ,  H05K2203/087 ,  Y10T29/49162

Abstract: A printed circuit board includes a substrate, and a wiring provided on the substrate. The wiring includes a copper-based metal wire provided on the substrate and a surface-treated layer provided on the copper-based metal wire. The copper-based metal wire includes mainly a copper. The surface-treated layer includes an amorphous layer including oxygen and a metal with a higher oxygen affinity than the copper.

公开(公告)号：US20160379951A9

公开(公告)日：2016-12-29

申请号：US14566185

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： RAJASEKARAN SWAMINATHAN ,  RAVINDRANATH V. MAHAJAN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11418 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13316 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13387 ,  H01L2224/13411 ,  H01L2224/13447 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/75264 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81222 ,  H01L2224/81409 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/3494 ,  H05K2201/0341 ,  H05K2201/083 ,  H05K2201/10674 ,  H05K2203/104 ,  Y02P70/613 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05381 ,  H01L2924/053 ,  H01L2924/0532 ,  H01L2924/01056

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.

Abstract translation: 本公开涉及制造微电子封装的领域，其中分布在焊膏内的磁性颗粒可用于形成磁性金属间化合物互连。 金属间化合物互连可以暴露于磁场，磁场可以将焊料材料加热到回流温度，以附接包括微电子封装的微电子部件。

公开(公告)号：US20160270237A1

公开(公告)日：2016-09-15

申请号：US15063497

申请日：2016-03-07

Applicant: Lam Research Corporation

Inventor： Byung Jin Cho ,  Seong Jun Yoon ,  Hyungsuk Alexander Yoon

IPC: H05K3/28 ,  H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H05K3/14 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/285 ,  H01L21/0331 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H05K1/0306 ,  H05K3/107 ,  H05K2201/0341 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2203/095 ,  H05K2203/1361 ,  H05K2203/1366

Abstract: Disclosed is a copper interconnection device including a surface-functionalized graphene capping layer and a method of fabricating the same, wherein electromigration of a fine copper interconnection can be suppressed by the capping layer having a thickness of ones of nm or less. Specifically, graphene is surface-functionalized to possess functional groups able to chemically interact with copper atoms and is thus used as the capping layer, whereby it is difficult to move the copper atoms through the chemical interaction with the functional groups by the use of only the capping layer as thin as ones of nm or less, effectively suppressing electromigration of the copper interconnection.

Abstract translation: 公开了一种包括表面官能化石墨烯覆盖层的铜互连装置及其制造方法，其中可以通过具有nm以下的厚度的覆盖层来抑制细铜互连的电迁移。 具体地，石墨烯被表面官能化以具有能够与铜原子化学相互作用的官能团，因此被用作封盖层，由此难以使铜原子通过与官能团的化学相互作用而移动，仅使用 覆盖层薄到nm以下，有效地抑制铜互连的电迁移。

公开(公告)号：US20160081199A1

公开(公告)日：2016-03-17

申请号：US14794559

申请日：2015-07-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jung Youn KIM

IPC: H05K3/40 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K3/3484 ,  H01L24/00 ,  H05K2201/0341 ,  H05K2201/10378 ,  H05K2203/043

Abstract: A manufacturing method of a printed circuit board (PCB), including: forming a conductive metal layer on a substrate having conductive pads exposed on one surface of the substrate; melting the conductive metal layer in a heat treatment; and forming solder bumps by concentrating portions of the melted conductive metal layer on the conductive pads, respectively.

Abstract translation: 一种印刷电路板（PCB）的制造方法，包括：在具有在衬底的一个表面上暴露的导电焊盘的衬底上形成导电金属层; 在热处理中熔化导电金属层; 以及通过将熔融的导电金属层的部分分别集中在导电焊盘上来形成焊料凸块。

公开(公告)号：US09288901B2

公开(公告)日：2016-03-15

申请号：US14264499

申请日：2014-04-29

Applicant: Roger G. Markham ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

Inventor： Roger G. Markham ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

IPC: H01L33/42 ,  H05K1/02 ,  H01B1/02 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K1/0298 ,  H01B1/02 ,  H05K1/0293 ,  H05K1/097 ,  H05K1/165 ,  H05K3/103 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/181 ,  H05K3/246 ,  H05K3/247 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/10098 ,  H05K2203/1476 ,  H05K2203/173

Abstract: A thin-film multi-layer micro-wire structure includes a substrate and a layer located on the substrate or forming a part of the substrate. One or more micro-channels are located in the layer. Each micro-channel has a width less than or equal to 20 microns. A cured electrically conductive micro-wire is located only within each micro-channel. The micro-wire has a thickness less than or equal to 20 microns, including silver nano-particles, and having a percent ratio of silver that is greater than or equal to 40% by weight. An electrolessly plated layer is located at least partially within each micro-channel between the micro-wire and the layer surface and in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.

Abstract translation: 薄膜多层微线结构包括衬底和位于衬底上或形成衬底的一部分的层。 一个或多个微通道位于该层中。 每个微通道具有小于或等于20微米的宽度。 固化的导电微线仅位于每个微通道内。 微线具有小于或等于20微米的厚度，包括银纳米颗粒，并且银的百分比大于或等于40重量％。 无电镀层至少部分地位于微线和层表面之间的每个微通道内并与微线电接触。 电镀层的厚度小于微线的厚度，使得微线和镀层形成薄膜多层微线。

公开(公告)号：US20150334832A1

公开(公告)日：2015-11-19

申请号：US14598595

申请日：2015-01-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Min BAEK ,  Yoon Su KIM ,  Jin Hyuck YANG ,  Chang Bae LEE

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/40

CPC classification number: H05K1/111 ,  H05K3/108 ,  H05K3/188 ,  H05K3/388 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/09381 ,  H05K2203/0713 ,  H05K2203/0716 ,  H05K2203/0723 ,  H05K2203/1407 ,  Y10T428/12396

Abstract: The present invention relates to an electrode structure which includes: a base substrate; a seed layer provided on one or both surfaces of the base substrate; an electroplating layer provided on the seed layer; and barriers discontinuously provided between the seed layer and the electroplating layer.

Abstract translation: 本发明涉及电极结构，其包括：基底; 种子层，设置在所述基底基板的一个或两个表面上; 设置在种子层上的电镀层; 并且在种子层和电镀层之间不连续地提供阻挡层。

公开(公告)号：US20150313009A1

公开(公告)日：2015-10-29

申请号：US14264499

申请日：2014-04-29

Applicant: ROGER G. MARKHAM ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

Inventor： ROGER G. MARKHAM ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/18 ,  H01B1/02

CPC classification number: H05K1/0298 ,  H01B1/02 ,  H05K1/0293 ,  H05K1/097 ,  H05K1/165 ,  H05K3/103 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/181 ,  H05K3/246 ,  H05K3/247 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/10098 ,  H05K2203/1476 ,  H05K2203/173

Abstract: A thin-film multi-layer micro-wire structure includes a substrate and a layer located on the substrate or forming a part of the substrate. One or more micro-channels are located in the layer. Each micro-channel has a width less than or equal to 20 microns. A cured electrically conductive micro-wire is located only within each micro-channel. The micro-wire has a thickness less than or equal to 20 microns, including silver nano-particles, and having a percent ratio of silver that is greater than or equal to 40% by weight. An electrolessly plated layer is located at least partially within each micro-channel between the micro-wire and the layer surface and in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.

Abstract translation: 薄膜多层微线结构包括衬底和位于衬底上或形成衬底的一部分的层。 一个或多个微通道位于该层中。 每个微通道具有小于或等于20微米的宽度。 固化的导电微线仅位于每个微通道内。 微线具有小于或等于20微米的厚度，包括银纳米颗粒，并且银的百分比大于或等于40重量％。 无电镀层至少部分地位于微线和层表面之间的每个微通道内并与微线电接触。 电镀层的厚度小于微线的厚度，使得微线和镀层形成薄膜多层微线。

公开(公告)号：US20150289380A1

公开(公告)日：2015-10-08

申请号：US14741545

申请日：2015-06-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kotaro KODANI ,  Kentaro KANEKO ,  Kazuhiro KOBAYASHI

IPC: H05K3/10

CPC classification number: H05K3/10 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15174 ,  H05K1/113 ,  H05K3/00 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/1184 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.

Abstract translation: 布线基板包括具有第一表面和位于与第一表面相反一侧的第二表面的电极焊盘，连接到电极焊盘的第一表面的导体图案，以及嵌入电极焊盘和导体的绝缘体层 模式。 绝缘体层覆盖电极焊盘的第二表面的外周部。

公开(公告)号：US09142501B2

公开(公告)日：2015-09-22

申请号：US14447908

申请日：2014-07-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Minhua Lu ,  Eric D. Perfecto ,  David J. Russell ,  Wolfgang Sauter ,  Krystyna Semkow ,  Thomas A. Wassick

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/768 ,  H05K1/09 ,  H05K3/40 ,  H05K3/34

CPC classification number: H01L23/49816 ,  H01L21/76843 ,  H01L21/76885 ,  H01L23/49866 ,  H01L2224/11 ,  H05K1/09 ,  H05K3/3478 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/09745 ,  H05K2203/041

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract translation: 一种互连结构，其包括其中存在电气部件的基板以及与接触焊盘接触的凸起下冶金（UBM）堆叠，所述凸块冶金（UBM）堆叠存在于所述基板中的所述电气部件。 UBM堆叠包括与接触焊盘直接接触电气部件的金属粘合层，与金属粘附层层直接接触的铜（Cu）种子层，第一镍（Ni）阻挡层， 存在于铜（Cu）种子层的直接接触中，以及存在于第一镍（Ni）阻挡层上的至少一个铜（Cu）导体层和至少一个第二镍（Ni）阻挡层的层状结构。 第二镍（Ni）阻挡层上可能存在焊球。