公开(公告)号：US07312523B2

公开(公告)日：2007-12-25

申请号：US11161285

申请日：2005-07-28

Applicant: Jean J. Audet ,  Jon A. Casey ,  Luc Guerin ,  David L. Questad ,  David J. Russell

Inventor： Jean J. Audet ,  Jon A. Casey ,  Luc Guerin ,  David L. Questad ,  David J. Russell

IPC: H01L23/053 ,  H01L23/12 ,  H01L23/48

CPC classification number: H05K1/116 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2924/00

Abstract: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 μm. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 μm. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

Abstract translation: 电路板包括填充树脂的电镀（RFP）通孔; 在RFP通孔上的电介质层; 电介质层中的大致圆形的RFP帽，并连接到RFP通孔的上部开口; 电介质层中的通孔叠层; 以及从所述通孔叠层径向向外延伸的多个通孔焊盘，其中所述多个通路焊盘中的每一个在径向上大于所述RFP盖。 优选地，RFP帽包括至少300μm的直径。 优选地，每个通孔焊盘包括具有至少400μm直径的基本圆形形状。 此外，电路板还包括连接到通孔叠层的球栅阵列垫; 以及连接到球栅阵列垫的输入/输出球栅阵列垫。 此外，电路板还包括电介质层中的金属平面。

公开(公告)号：US07298331B2

公开(公告)日：2007-11-20

申请号：US11201479

申请日：2005-08-11

Applicant: Robert R. Oberly

Inventor： Robert R. Oberly

IPC: H01Q1/38

CPC classification number: H01Q7/00 ,  H01Q1/38 ,  H01Q9/27 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/165 ,  H05K3/242 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2203/1476 ,  H05K2203/1545

Abstract: A metalized circuit suitable for application as a radio frequency antenna is produced by forming an antenna coil pattern on a flexible substrate. The antenna coil pattern is formed using a conductive ink which is patterned on the substrate. The conductive ink is cured and an electrical-short layer is formed across the coils of the conductive ink pattern. An insulating layer is formed over top of the electrical-short layer, a metal layer electroplated on top of the conductive layer, and then the electrical-short layer is removed. The use of the electrical-short layer during the electroplating allows for the voltage at the different points on the conductive ink layer to be relatively similar, so that a uniform electroplate layer is formed on top of the conductive ink layer. This results in a better quality radio frequency antenna at a reduced cost.

公开(公告)号：US07253029B2

公开(公告)日：2007-08-07

申请号：US10797457

申请日：2004-03-10

Applicant: Carl Geisler ,  Dennis O'Keefe

Inventor： Carl Geisler ,  Dennis O'Keefe

IPC: H01L23/495 ,  H01L23/10 ,  H01L23/06

CPC classification number: B81C1/00269 ,  H01L21/50 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H05K1/092 ,  H05K3/246 ,  H05K2201/0347 ,  H01L2924/00

Abstract: A process for preparing an electronic package comprising: (a) providing a ceramic housing defining an internal cavity for receiving a micro device and having one or more interface portions; (b) treating the housing to form a tungsten layer on the interface portions; and (c) overlaying a palladium layer on the tungsten layer.

Abstract translation: 一种用于制备电子封装的方法，包括：（a）提供限定用于接收微型装置并具有一个或多个界面部分的内部空腔的陶瓷壳体; （b）处理所述壳体以在所述界面部分上形成钨层; 和（c）在钨层上覆盖钯层。

公开(公告)号：US20070176302A1

公开(公告)日：2007-08-02

申请号：US11643693

申请日：2006-12-22

Applicant: Tae Soo Lee ,  Yun Hwi Park ,  Taek Jung Lee

Inventor： Tae Soo Lee ,  Yun Hwi Park ,  Taek Jung Lee

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K3/246 ,  H05K3/341 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00

Abstract: An LTCC module includes an LTCC substrate and a pad part formed on an undersurface of the LTCC substrate for mounting the LTCC substrate to an external substrate. The pad part includes a metal pad layer formed on an undersurface of the LTCC substrate and a solder layer formed on an undersurface of the metal pad layer.

Abstract translation: LTCC模块包括LTCC基板和形成在LTCC基板的下表面上的焊盘部分，用于将LTCC基板安装到外部基板。 焊盘部分包括形成在LTCC衬底的下表面上的金属焊盘层和形成在金属焊盘层的下表面上的焊料层。

公开(公告)号：US20070131449A1

公开(公告)日：2007-06-14

申请号：US11634868

申请日：2006-12-07

Applicant: Yasuhito Funada ,  Jun Ishii

Inventor： Yasuhito Funada ,  Jun Ishii

IPC: H05K1/00

CPC classification number: H05K1/0269 ,  H05K1/056 ,  H05K3/44 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/0723

Abstract: A wired circuit board and a producing method thereof are provided which can precisely form an insulating layer and reduce transmission loss with a simple layer structure and also features excellent long-term reliability by preventing the occurrence of an ion migration phenomenon between a ground layer and a positioning mark layer, and the insulating layer to improve the adhesion therebetween and the conductivity of a conductor. A metal supporting board is prepared and a first metal thin film is formed on the metal supporting board. A resist is formed in a pattern and a ground layer and a positioning mark layer are formed on the first metal thin film exposed from the resist at the same time. A second metal thin film is formed over the ground layer and the positioning mark layer, then the resist is removed. An insulating base layer is formed on the first metal thin film including the upper surface of the second metal thin film, thereafter, a conductive pattern is formed on the insulating base layer.

Abstract translation: 提供一种布线电路板及其制造方法，其可以精确地形成绝缘层，并且以简单的层结构减小传输损耗，并且还通过防止接地层和接地层之间的离子迁移现象的发生而具有优异的长期可靠性 定位标记层和绝缘层，以改善其间的粘附性和导体的导电性。 制备金属支撑板，在金属支撑板上形成第一金属薄膜。 在图案中形成抗蚀剂，同时在从抗蚀剂暴露的第一金属薄膜上形成接地层和定位标记层。 在接地层和定位标记层上形成第二金属薄膜，然后除去抗蚀剂。 在包括第二金属薄膜的上表面的第一金属薄膜上形成绝缘基底层，之后在绝缘基底层上形成导电图案。

公开(公告)号：US20070097596A1

公开(公告)日：2007-05-03

申请号：US11583067

申请日：2006-10-19

Applicant: Hajime Kuwajima ,  Masahiro Miyazaki ,  Akira Furuya

Inventor： Hajime Kuwajima ,  Masahiro Miyazaki ,  Akira Furuya

IPC: H01G4/06

CPC classification number: H01G4/33 ,  H01G4/01 ,  H05K1/162 ,  H05K3/244 ,  H05K2201/0179 ,  H05K2201/0347 ,  Y10T29/435

Abstract: A thin-film device comprises a substrate and a capacitor provided on the substrate. The capacitor incorporates: a lower conductor layer disposed on the substrate; a dielectric film disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The thickness of the dielectric film falls within a range of 0.02 to 1 μm inclusive and is smaller than the thickness of the lower conductor layer. The surface roughness in maximum height of the top surface of the lower conductor layer is equal to or smaller than the thickness of the dielectric film.

Abstract translation: 薄膜器件包括衬底和设置在衬底上的电容器。 电容器包括：设置在基板上的下导体层; 设置在下导体层上的电介质膜; 以及设置在电介质膜上的上导体层。 电介质膜的厚度在0.02〜1μm的范围内，小于下导体层的厚度。 下导体层的上表面的最大高度的表面粗糙度等于或小于电介质膜的厚度。

公开(公告)号：US20060283005A1

公开(公告)日：2006-12-21

申请号：US11509862

申请日：2006-08-25

Applicant: James Coleman ,  Scott Ferguson ,  Jaime Grunlan ,  Ian Forster ,  Andrew Holman ,  Peikang Liu

Inventor： James Coleman ,  Scott Ferguson ,  Jaime Grunlan ,  Ian Forster ,  Andrew Holman ,  Peikang Liu

IPC: B05D5/12 ,  B32B37/00 ,  H01P11/00

CPC classification number: H01L23/49855 ,  G06K19/07749 ,  H01L21/4846 ,  H01L24/95 ,  H01L2224/95085 ,  H05K1/095 ,  H05K1/165 ,  H05K3/205 ,  H05K3/32 ,  H05K3/386 ,  H05K2201/0347 ,  H05K2203/1469 ,  H05K2203/1545 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T156/1062

Abstract: A method of forming an electrically-conductive pattern includes selectively electroplating the top portions of a substrate that corresponds to the pattern, and separating the conductive pattern from the substrate. The electroplating may also include electrically connecting the conductive pattern to an electrical component. Conductive ink, such as ink including carbon particles, may be selectively placed on the conductive substrate to facilitate plating of the desired pattern and/or to facilitate separation of the pattern from the substrate. An example of a conductive pattern is an antenna for a radio-frequency identification (RFID) device such as a label or a tag. One example of an electrical component that may be electrically connected to the antenna, is an RFID strap or chip.

公开(公告)号：US07105070B2

公开(公告)日：2006-09-12

申请号：US10935164

申请日：2004-09-08

Applicant: Akifumi Tosa ,  Jun Otsuka ,  Manabu Sato ,  Hisahito Kashima

Inventor： Akifumi Tosa ,  Jun Otsuka ,  Manabu Sato ,  Hisahito Kashima

IPC: B32B37/06 ,  B32B38/10 ,  C03B29/00 ,  H05K3/26 ,  H05K3/46

CPC classification number: B32B18/00 ,  C03C14/004 ,  C03C2214/20 ,  C04B2235/6567 ,  C04B2235/9615 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/56 ,  C04B2237/562 ,  C04B2237/565 ,  C04B2237/568 ,  C04B2237/66 ,  C04B2237/68 ,  C04B2237/702 ,  C04B2237/704 ,  H01G4/30 ,  H01L21/481 ,  H01L21/4857 ,  H05K1/0306 ,  H05K3/246 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2201/09881 ,  H05K2203/308

Abstract: A method for producing a ceramic substrate which employs a cofiring process using restraint sheets in which a second ceramic green sheet 7 is laminated on a green ceramic substrate 30 so as to cover surface conductors 32 of the green ceramic substrate 30, the second ceramic green sheet 7 subsequently being integrated with the green ceramic substrate 30. Restraint sheets 9, which are not sintered at a sintering temperature at which the green ceramic substrate 30 is sintered, are laminated on corresponding opposite sides of the green ceramic substrate 30 so as to restrain the green ceramic substrate 30 together with the second ceramic green sheet 7. The second ceramic green sheet 7 and the green ceramic substrate 30 are fired at a temperature at which the second ceramic green sheet 7 and the green ceramic substrate 30 are integrally sintered, whereas the restraint sheets 9 are not sintered, to thereby yield a ceramic substrate 40. The restraint sheets 9 and a ceramic covering layer 7a which covers the surface conductors 32 are removed, to thereby expose the surface conductor layer 32. A plating layer 31 is formed on the surface conductor layer 32.

Abstract translation: 一种陶瓷基板的制造方法，其使用使用在生陶瓷基板30上层叠有第二陶瓷生片7以将陶瓷基板30的表面导体32覆盖的第二陶瓷生片的约束片， 7随后与绿色陶瓷基板30集成。 在烧结生坯陶瓷基板30的烧结温度下没有烧结的约束片9层叠在生陶瓷基板30的对应的相对侧，以便与第二陶瓷生片一起抑制生陶瓷基板30 7。 第二陶瓷生片7和生陶瓷基片30在第二陶瓷生片7和生陶瓷基片30一体烧结的温度下烧制，而约束片9不烧结，从而产生陶瓷基片 40。 去除约束片9和覆盖表面导体32的陶瓷覆盖层7a，从而露出表面导体层32。 在表面导体层32上形成镀层31。

公开(公告)号：US20060183316A1

公开(公告)日：2006-08-17

申请号：US11397713

申请日：2006-04-05

Applicant: James Larnerd ,  John Lauffer ,  Voya Markovich ,  Kostas Papathomas

Inventor： James Larnerd ,  John Lauffer ,  Voya Markovich ,  Kostas Papathomas

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

Abstract translation: 一种制造印刷电路板的方法，其中导电通孔形成在板结构的两个电介质层内，以便连接指定的导电层。 一个孔连接两个相邻的层，另一个连接两个相邻的层，包括通过另一个孔连接的一个导电层。 也可以使用一个或多个孔连接所有三个导电层。 所得到的孔可以例如用金属电镀或导电或不导电的糊料填充。 在后者的情况下，也可以在浆料上方设置顶部覆盖导电层，例如在板的外表面上用作衬垫等。

公开(公告)号：US20060174477A1

公开(公告)日：2006-08-10

申请号：US11400289

申请日：2006-04-10

Applicant: Koichi Tanaka

Inventor： Koichi Tanaka

IPC: H01C17/06 ,  H05K3/10

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K2201/0347 ,  H05K2201/09763 ,  H05K2203/1453 ,  H05K2203/171 ,  Y10T29/49098 ,  Y10T29/49099 ,  Y10T29/49155

Abstract: A wiring board provided with a resistor comprises: an insulating substrate having a surface; wiring patterns formed on the surface, the wiring patterns including first and second electrodes spaced from each other by a certain distance; a first resistor (horizontal type resistor) formed on the surface, the first resistor having respective ends connected with the first and second electrodes, respectively; the wiring patterns further including a third electrode, occupying a first plane area on the surface; a second resistor (vertical type resistor) formed on the third electrode; a fourth electrode formed on the second resistor; and the second resistor and the fourth electrode being located in a second plane area within the first plane area.

Abstract translation: 设置有电阻器的布线板包括：具有表面的绝缘基板; 布线图案形成在表面上，布线图案包括彼此隔开一定距离的第一和第二电极; 形成在所述表面上的第一电阻器（水平型电阻器），所述第一电阻器分别具有与所述第一和第二电极连接的端部; 所述布线图形还包括占据所述表面上的第一平面区域的第三电极; 形成在第三电极上的第二电阻器（垂直型电阻器） 形成在所述第二电阻器上的第四电极; 并且所述第二电阻器和所述第四电极位于所述第一平面区域内的第二平面区域中。