公开(公告)号：US09213139B2

公开(公告)日：2015-12-15

申请号：US14097812

申请日：2013-12-05

Applicant: Ronald Steven Cok ,  Todd Mathew Spath

Inventor： Ronald Steven Cok ,  Todd Mathew Spath

IPC: H01L31/12 ,  H01L31/18 ,  G02B6/13 ,  G02B6/122 ,  H05K3/12 ,  H01L23/538 ,  H01L21/768 ,  G02B6/42 ,  G06F3/044 ,  H05K3/32 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/138 ,  G02B6/4214 ,  G02B6/4274 ,  G02B2006/121 ,  G02B2006/12104 ,  G02B2006/12126 ,  G02B2006/12147 ,  G06F3/044 ,  H01L21/76895 ,  H01L23/5386 ,  H01L31/12 ,  H01L31/18 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/10 ,  H05K3/101 ,  H05K3/1258 ,  H05K3/32 ,  H05K2201/0108 ,  H05K2201/09036 ,  H05K2201/10356 ,  H05K2203/0108 ,  H01L2924/00

Abstract: A method of making an imprinted optical micro-channel structure for transmitting light to an optical receiver or receiving light from an optical transmitter includes forming a curable optical layer over a substrate and imprinting one or more optical micro-channels in the optical layer with a first stamp. The curable optical layer is cured to form a cured optical layer having the optical micro-channels imprinted in the cured optical layer. A curable light-transparent material is located in the optical micro-channels and cured to form light-pipes of cured light-transparent material in the optical micro-channels. The optical transmitter located in alignment with a light-pipe for transmitting light through the light-pipe or the optical receiver is located in alignment with a light-pipe for receiving light from the light-pipe.

Abstract translation: 一种制造用于将光传输到光接收器或从光发射器接收光的压印光学微通道结构的方法包括在衬底上形成可固化的光学层，并在第一个光学层中将一个或多个光学微通道压印在光学层中 邮票。 固化光学层被固化以形成固化的光学层，该光学层具有印刷在固化的光学层中的光学微通道。 可光固化的透光材料位于光学微通道中并固化，以在光学微通道中形成固化的透光材料的光管。 与用于透过光管或光接收器透射光的光管对准的光发射器与用于接收来自光管的光的光管对准。

公开(公告)号：US09210808B2

公开(公告)日：2015-12-08

申请号：US13616348

申请日：2012-09-14

Applicant: Kentaro Kaneko ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

Inventor： Kentaro Kaneko ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/00 ,  H01L23/544 ,  H01L21/683 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/188 ,  C25D5/022 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/0017 ,  H05K3/46 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/06 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.

Abstract translation: 布线基板包括绝缘层，埋置在绝缘层中的连接焊盘，该连接焊盘处于连接焊盘的上表面从绝缘层的上表面露出的状态以及下表面和侧表面的至少一部分 所述连接焊盘与所述绝缘层接触，以及形成在所述绝缘层中的所述连接焊盘的外周部分的凹陷高度差部分，其中所述连接焊盘的上表面和所述绝缘层的上表面被布置在 相同的高度

公开(公告)号：US20150342049A1

公开(公告)日：2015-11-26

申请号：US14718368

申请日：2015-05-21

Applicant: KYOCERA CIRCUIT SOLUTIONS, INC.

Inventor： Tomoharu TSUCHIDA ,  Kazuki OKA ,  Daichi OHMAE

IPC: H05K1/14 ,  H05K3/36 ,  H01L21/78 ,  H05K3/10

CPC classification number: H05K1/142 ,  H01L21/78 ,  H01L2224/11 ,  H05K3/0097 ,  H05K3/10 ,  H05K3/36 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09154 ,  H05K2203/0169 ,  Y10T29/303 ,  Y10T29/49163

Abstract: The multi-piece, wiring board according to the embodiment of the present invention includes a supporting board including a frame portion formed on an upper surface of a bottom plate, the frame portion configured to divide the upper surface of the bottom plate into a plurality of product forming regions, and a wiring board formed on the upper surface of the bottom plate in. each of the product forming regions, the: wiring board including an insulating layer formed so as to expose an upper surface of the frame portion, and a wiring conductor formed on the insulating layer.

Abstract translation: 根据本发明的实施例的多片式布线板包括支撑板，该支撑板包括形成在底板的上表面上的框架部分，框架部分被构造成将底板的上表面分成多个 产品形成区域和形成在每个产品形成区域的底板的上表面上的布线板，所述布线板包括形成为暴露框架部分的上表面的绝缘层，以及布线 导体形成在绝缘层上。

公开(公告)号：US20150340785A1

公开(公告)日：2015-11-26

申请号：US14652463

申请日：2013-12-11

Applicant: NEC CORPORATION

Inventor： Kazuhiro KASHIWAKURA

IPC: H01R12/72 ,  H01R13/6473 ,  H01R13/6461

CPC classification number: H05K1/117 ,  H01R12/721 ,  H01R12/73 ,  H01R13/6461 ,  H01R13/6473 ,  H05K1/024 ,  H05K1/025 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09709

Abstract: An electronic substrate 100 includes: a substrate member 110 which has a shape of plane plate and whose pair of main surfaces 110a and 110b are opposite each other; a plurality of connection terminals 130 which are formed so as to be arranged on an edge side of the substrate member 110 and on at least one surface out of the pair of main surfaces 110a and 110b of the substrate member 110; a plurality of wirings 120 which are connected with the plural connection terminals 130; and a plurality of openings 140A arranged in an area, which exists between connection terminals 130 adjacent each other out of the plural connection terminals 130 and in which the connection terminals 130 adjacent each other extend, in an extending direction of the connection terminals 130 adjacent each other.

Abstract translation: 电子基板100包括：基板构件110，其具有平面板的形状，并且其一对主表面110a和110b彼此相对; 多个连接端子130，其被形成为布置在基板部件110的边缘侧以及基板部件110的一对主表面110a和110b中的至少一个表面上; 与多个连接端子130连接的多个布线120; 以及布置在区域中的多个开口140A，其位于多个连接端子130中彼此相邻的连接端子130之间，并且彼此相邻的连接端子130在每个相邻的连接端子130的延伸方向上延伸。 其他。

公开(公告)号：US09177821B2

公开(公告)日：2015-11-03

申请号：US14259042

申请日：2014-04-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Soon-Won Jung ,  Jae Bon Koo ,  Chan Woo Park ,  Bock Soon Na ,  Sang Chul Lim ,  Sang Seok Lee ,  Kyoung Ik Cho ,  Hye Yong Chu

IPC: H01L21/338 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/311 ,  G09F9/301 ,  H01L29/66477 ,  H01L51/0023 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/102 ,  H05K1/0283 ,  H05K1/0333 ,  H05K1/16 ,  H05K3/0017 ,  H05K3/007 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10166 ,  H05K2201/2009 ,  H05K2203/308

Abstract: Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.

Abstract translation: 提供一种制造电子电路的方法。 该方法包括制备基底，在基底上形成聚合物膜，图案化聚合物膜以形成聚合物图案，并在聚合物图案上形成电子器件。

公开(公告)号：US09171809B2

公开(公告)日：2015-10-27

申请号：US14198399

申请日：2014-03-05

Applicant: Flextronics AP, LLC

Inventor： Omar Garcia Lopez ,  Pedro Alejandro Ahumada Quintero ,  Enrique Avelar Secada ,  Murad Kurwa ,  Juan Carlos Gonzalez

IPC: H01L23/495 ,  H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  H05K3/34 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L24/83 ,  H01L2224/26122 ,  H01L2224/291 ,  H01L2224/83815 ,  H01L2924/1011 ,  H01L2924/12042 ,  H01L2924/15151 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09036 ,  H05K2201/10969 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation.

Abstract translation: 用于在焊点形成过程中产生的焊剂和气体远离焊点移动的漏斗路径的方法和装置。

公开(公告)号：US20150296616A1

公开(公告)日：2015-10-15

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

Abstract translation: 一些新颖特征涉及包括第一介电层，第一互连，第一空腔和第一无电金属层的基板。 第一电介质层包括第一表面和第二表面。 第一互连在衬底层的第一表面上。 第一空腔穿过第一介电层的第一表面。 第一无电金属层至少部分地形成在第一腔中。 第一无电金属层限定嵌入在第一介电层中的第二互连。 在一些实施方案中，衬底还包括芯层。 芯层包括第一表面和第二表面。 芯层的第一表面耦合到第一介电层的第二表面。 在一些实施方案中，衬底还包括第二介电层。

公开(公告)号：US09159658B2

公开(公告)日：2015-10-13

申请号：US14005105

申请日：2012-03-16

Applicant: Reimund Oberschmid

Inventor： Reimund Oberschmid

IPC: H05K1/02 ,  H01L23/498 ,  H01L33/62 ,  H01L33/64 ,  H05K1/11

CPC classification number: H01L23/498 ,  H01L23/49811 ,  H01L33/62 ,  H01L33/647 ,  H01L2224/16225 ,  H01L2224/81385 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K1/111 ,  H05K2201/0133 ,  H05K2201/09036 ,  H05K2201/09263 ,  H05K2201/10106 ,  H01L2924/00

Abstract: A connection carrier for at least one semiconductor chip is disclosed. The connection carrier has a carrier body having a main surface. A first connection area and a second connection area at a distance from the first connection area are formed on the main surface. The connection carrier has a mechanical decoupling device which is intended to reduce transmission of mechanical forces from the carrier body to at least one region of the first connection area. A semiconductor component having such a connection carrier is also stated.

Abstract translation: 公开了一种用于至少一个半导体芯片的连接载体。 连接托架具有主体，主体具有主表面。 在主表面上形成有距离第一连接区域一定距离的第一连接区域和第二连接区域。 连接载体具有机械解耦装置，其旨在减少机械力从载体主体到第一连接区域的至少一个区域的传递。 还描述了具有这种连接载体的半导体部件。

公开(公告)号：US20150289370A1

公开(公告)日：2015-10-08

申请号：US14000186

申请日：2012-12-20

Applicant: NANCHANG O-FILM TECH. CO., LTD.

Inventor： Yulong Gao ,  Zheng Cui ,  Hongwei Kang

IPC: H05K1/11 ,  H05K3/10 ,  H05K1/02

CPC classification number: H05K1/11 ,  H01L31/022466 ,  H01L31/1884 ,  H05K1/0274 ,  H05K1/092 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/09036 ,  H05K2201/09681 ,  H05K2203/0514 ,  H05K2203/0545 ,  Y02E10/50 ,  Y10T29/49155

Abstract: A double-sided patterned transparent conductive film includes an upper surface conductive layer (12) and a lower surface conductive layer (12). The upper surface conductive layer is a patterned trench network; the lower surface conductive layer is a full-surface trench network. A trench of the upper surface conductive layer is filled with conductive material (13), and a trench of the lower surface conductive layer is intermittently filled with conductive material (13). The double-sided patterned transparent conductive film has a high resolution, transmittance, independently adjustable square resistance and many other advantages, such that the transparent conductive film saves a cost of PET. According to the manufacturing method, the alignment is not needed for double-sided imprinting of a single flexible substrate, thus the process is simple, low cost, advantageous for industrial production.

Abstract translation: 双面图案化的透明导电膜包括上表面导电层（12）和下表面导电层（12）。 上表面导电层是图案化的沟槽网络; 下表面导电层是全表面沟槽网络。 上表面导电层的沟槽填充有导电材料（13），并且下表面导电层的沟槽间歇地填充有导电材料（13）。 双面图案化的透明导电膜具有高分辨率，透射率，独立可调的方形电阻等许多优点，使得透明导电膜节省了PET的成本。 根据制造方法，对于单个柔性基板的双面印刷不需要对准，因此该工艺简单，成本低，对于工业生产是有利的。

公开(公告)号：US20150282305A1

公开(公告)日：2015-10-01

申请号：US14669329

申请日：2015-03-26

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka SHIMABE ,  Shunsuke SAKAI

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K1/0284 ,  H01L21/568 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2924/15313 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/09145 ,  H05K2201/09154 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A multilayer wiring board with a built-in electronic component includes a substrate, a conductor layer formed on surface of the substrate, one or more electronic components positioned in a cavity formed through the substrate, an insulating layer formed on the substrate such that the insulating layer is formed on the component in the cavity, and a wiring layer formed on the insulating layer. The conductor layer has an opening formed such that the cavity is formed in the opening of the conductor layer and that the conductor layer has a first side in the opening and a second side in the opening on the opposite side across the cavity, and the cavity is formed in the opening of the conductor layer such that width between the cavity and the first side of the conductor layer is greater than width between the cavity and the second side of the conductor layer.

Abstract translation: 具有内置电子部件的多层布线基板包括基板，形成在基板的表面上的导体层，位于通过基板形成的空腔中的一个或多个电子部件，形成在基板上的绝缘层， 在空腔中的部件上形成层，以及形成在绝缘层上的布线层。 导体层具有形成为使得空腔形成在导体层的开口中并且导体层在开口中具有第一侧的开口，并且在开口中的相对于空腔的开口中的第二侧，并且空腔 形成在导体层的开口中，使得空腔和导体层的第一侧之间的宽度大于导体层的空腔和第二侧之间的宽度。