公开(公告)号：US20080315437A1

公开(公告)日：2008-12-25

申请号：US12222986

申请日：2008-08-21

Applicant: Si-Hoon Lee ,  Eun-Seok Song

Inventor： Si-Hoon Lee ,  Eun-Seok Song

IPC: H01L23/52

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

公开(公告)号：US20080278858A1

公开(公告)日：2008-11-13

申请号：US12149903

申请日：2008-05-09

Applicant: Jun Ishii ,  Takahiko Yokai

Inventor： Jun Ishii ,  Takahiko Yokai

IPC: G11B5/48 ,  H05K1/03

CPC classification number: H05K1/0253 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/056 ,  H05K3/4644 ,  H05K2201/09081 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: The wired circuit board includes a metal supporting board, a metal foil formed on the metal supporting board, a first insulating layer formed on the metal supporting board so as to cover the metal foil, and a conductive pattern formed on the first insulating layer and having a plurality of wires. The metal foil is arranged along a lengthwise direction of each of the wires so as not to be opposed to part of the wires in a thickness direction and so as to be opposed to a remainder of the wires in the thickness direction.

Abstract translation: 布线电路板包括金属支撑板，形成在金属支撑板上的金属箔，形成在金属支撑板上以覆盖金属箔的第一绝缘层和形成在第一绝缘层上的导电图案，并且具有 多条电线。 金属箔沿着每条电线的长度方向布置，以便在厚度方向上不与电线的一部分相对，并且在厚度方向上与其余电线相对。

公开(公告)号：US07378936B2

公开(公告)日：2008-05-27

申请号：US11135762

申请日：2005-05-23

Applicant: Devin Bingham ,  Daniel J. Ayres ,  Alvin Chow

Inventor： Devin Bingham ,  Daniel J. Ayres ,  Alvin Chow

IPC: H01C10/00

CPC classification number: H05K1/162 ,  H05K1/0293 ,  H05K1/0298 ,  H05K3/027 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175

Abstract: A circuit element has a substrate layer with first and second faces. A conductive first layer overlays the first surface, and a conductive second layer overlays the second surface. The first layer defines a pattern with a trimmable portion. The second layer defines a pattern having a first conductive element registered with at least a portion of the trimmable portion, and a second conductive element electrically isolated from first element and encompassing the first element. The second element may be a ground plane that has an aperture surrounding the first component, which serves as a shield to prevent damage to any elements beyond the second layer.

Abstract translation: 电路元件具有带有第一和第二面的衬底层。 导电第一层覆盖第一表面，并且导电的第二层覆盖第二表面。 第一层定义具有可调节部分的图案。 第二层限定了具有与可调节部分的至少一部分配准的第一导电元件的图案，以及与第一元件电隔离并且包围第一元件的第二导电元件。 第二元件可以是具有围绕第一部件的孔的接地平面，其用作屏蔽件以防止损坏超出第二层的任何元件。

公开(公告)号：US20080116988A1

公开(公告)日：2008-05-22

申请号：US12009740

申请日：2008-01-22

Applicant: James Blair ,  Oswin Schreiber ,  Jeffrey Smith

Inventor： James Blair ,  Oswin Schreiber ,  Jeffrey Smith

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01P3/006 ,  H01P3/08 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/10492 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract translation: 用于电子组件的高速柔性互连电缆包括多个导电层和多个电介质层。 位于导电层上的导电信号迹线与电介质层结合形成一个或多个高速电传输线结构。 电缆可以使用各种连接技术耦合到电子元件。 电缆也可以用任何数量的已知或标准的连接器封装端接。

公开(公告)号：US07345889B1

公开(公告)日：2008-03-18

申请号：US10953775

申请日：2004-09-28

Applicant: David Norte

Inventor： David Norte

IPC: H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09318 ,  H05K2201/09781

Abstract: A method and system for reducing the release of high frequency electromagnetic energy into the environment is disclosed, wherein local regions of distributed capacitance are embedded within a printed circuit board (PCB) and adjacent the PCB conductive traces act as low pass filters and thus increase the rise and/or fall times occurring on such traces. The present invention increases very short rise and/or fall times (e.g., 200 picoseconds or less) without degrading or detrimentally affecting other signal characteristics. The present invention does not substantially affect the voltage amplitude and does not affect the bit period when lengthening the rise and/or fall time. Also, the present invention does not induce any timing jitter that may cause synchronization problems within the system.

Abstract translation: 公开了一种用于将高频电磁能释放到环境中的方法和系统，其中分布电容的局部区域嵌入在印刷电路板（PCB）中，并且邻近PCB导电迹线充当低通滤波器，因此增加 上升和/或下降时间发生在这样的痕迹上。 本发明增加非常短的上升和/或下降时间（例如，200皮秒或更少），而不降低或不利地影响其他信号特性。 本发明基本上不影响电压幅度，并且在延长上升和/或下降时间时不会影响位周期。 此外，本发明不会引起可能导致系统内的同步问题的任何定时抖动。

公开(公告)号：US20070102092A1

公开(公告)日：2007-05-10

申请号：US11272590

申请日：2005-11-10

Applicant: John Dangler ,  Matthew Doyle

Inventor： John Dangler ,  Matthew Doyle

IPC: B32B38/00 ,  B32B41/00

CPC classification number: B32B37/12 ,  B32B2457/08 ,  H05K1/0393 ,  H05K3/386 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0195 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09881

Abstract: A method for manufacturing multilayer flexible circuits is disclosed. The cross-sectional area of an unoccupied signal layer volume is initially determined. The unoccupied signal layer includes multiple conductive elements, and the unoccupied signal layer volume is formed between two of the conductive elements. Next, the thickness of an adhesive layer for filling the unoccupied signal layer volume is determined. Finally, the thickness of the adhesive layer is adjusted such that the adhesive layer only fills the unoccupied signal layer volume while the two conductive elements come in direct contact with a dielectric layer without any adhesive in between.

Abstract translation: 公开了一种制造多层柔性电路的方法。 初始确定未占用信号层体积的横截面面积。 未占用的信号层包括多个导电元件，并且在两个导电元件之间形成未占用的信号层体积。 接下来，确定用于填充未占用信号层体积的粘合剂层的厚度。 最后，调节粘合剂层的厚度，使得粘合剂层仅填充未占用的信号层体积，同时两个导电元件与电介质层直接接触，而两者之间没有任何粘合剂。

公开(公告)号：US20070058980A1

公开(公告)日：2007-03-15

申请号：US11496007

申请日：2006-07-31

Applicant: Hirotoshi Hidaka

Inventor： Hirotoshi Hidaka

IPC: H04B10/00

CPC classification number: G02B6/4201 ,  G02B6/4246 ,  G02B6/4277 ,  G02B6/4279 ,  G02B6/428 ,  G02B6/4281 ,  G02B6/4283 ,  H05K1/0218 ,  H05K1/147 ,  H05K2201/0715 ,  H05K2201/09318 ,  H05K2201/10121

Abstract: An influence of noise propagated from a transmitting circuit to a receiving circuit is reduced in an optical transceiver. The optical transceiver includes a transmitter optical subassembly (TOSA), a receiver optical subassembly (ROSA) including a light receiving element, a transmitting circuit for driving a light emitting element in TOSA, a receiving circuit for processing an electric signal from ROSA, and a printed circuit board mounted with the transmitting circuit and the receiving circuit. TOSA and ROSA are connected to the printed circuit board respectively by a first and a second flexible board. The printed circuit board includes a face mounted with the transmitting circuit. The second flexible board is provided with a ground layer at one face thereof and is provided with a signal line at a face on an opposed side. The second flexible board is arranged by directing the ground layer to a side of a face mounted with the transmitting circuit.

Abstract translation: 在光收发器中减少了从发射电路传播到接收电路的噪声的影响。 光收发器包括发射机光学子组件（TOSA），包括光接收元件的接收器光学子组件（ROSA），用于驱动TOSA中的发光元件的发射电路，用于处理来自ROSA的电信号的接收电路，以及 安装有发射电路和接收电路的印刷电路板。 TOSA和ROSA分别通过第一和第二柔性板连接到印刷电路板。 印刷电路板包括安装有发射电路的面。 第二柔性板在其一个面上设置有接地层，并且在相对侧的面处设置有信号线。 第二柔性板通过将接地层引导到安装有发射电路的面的一侧来布置。

公开(公告)号：US07110263B2

公开(公告)日：2006-09-19

申请号：US10797753

申请日：2004-03-09

Applicant: Jiangqi He ,  Joong-ho Kim ,  Hyunjun Kim ,  Dong-ho Han ,  Ping Sun

Inventor： Jiangqi He ,  Joong-ho Kim ,  Hyunjun Kim ,  Dong-ho Han ,  Ping Sun

IPC: H05K1/11

CPC classification number: H01P3/085 ,  H01P3/081 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09727

Abstract: An apparatus comprises a signal layer including a first and second signal trace. The apparatus also comprises a first reference plane including a first slot substantially parallel to the first and second signal traces. Further, the apparatus includes a dielectric layer having at least a portion disposed between the signal layer and the first reference plane.

Abstract translation: 一种装置包括包括第一和第二信号迹线的信号层。 该装置还包括第一参考平面，该第一参考平面包括基本上平行于第一和第二信号迹线的第一槽。 此外，该装置包括具有设置在信号层和第一参考平面之间的至少一部分的电介质层。

公开(公告)号：US07086869B1

公开(公告)日：2006-08-08

申请号：US11038708

申请日：2005-01-20

Applicant: John Richard Dangler ,  Matthew Stephen Doyle ,  Thomas Donald Kidd ,  Bradley Lewis Martin ,  Kevin J. Przybylski ,  Jason Thomas Stoll

Inventor： John Richard Dangler ,  Matthew Stephen Doyle ,  Thomas Donald Kidd ,  Bradley Lewis Martin ,  Kevin J. Przybylski ,  Jason Thomas Stoll

IPC: H01R12/00

CPC classification number: H05K1/0218 ,  H01B7/0861 ,  H05K1/0393 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0715 ,  H05K2201/09318 ,  H05K2201/09618

Abstract: In a flat flex cable, signal lines are surrounded by logic ground planes above and below which are viaed together left and right. The ground planes coupled with the flex cable dielectric determine characteristic the impedance and attenuation of the cable and provide differential signal EMI shielding. All signal layers and logic ground planes are enclosed within the two outermost shield layers which are viaed together left and right and around the connectors to enclose both signal layers and logic ground planes to provide common mode EMI shielding.

公开(公告)号：US20060110898A1

公开(公告)日：2006-05-25

申请号：US10991532

申请日：2004-11-19

Applicant: John Lauffer ,  Voya Markovich ,  Michael Wozniak

Inventor： John Lauffer ,  Voya Markovich ,  Michael Wozniak

IPC: H01L21/20

CPC classification number: H01L21/4857 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/383 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2203/0353 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/12556 ,  Y10T428/12993 ,  H01L2224/0401

Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

Abstract translation: 其中两个导电层（例如，电镀铜箔）被结合（例如层压）到电介质层的电路化衬底。 物理地结合到电介质的两个箔表面中的每一个是光滑的（例如，优选通过化学处理），并且在其上包括薄的有机层，而两个箔的外表面也是光滑的（例如，优选也使用化学处理 步）。 这些导电层中的一个可以用作接地或电压平面，而另一个可以用作具有多个单独信号线作为其一部分的信号平面。 还提供了利用这种电路化基板的电气组件和信息处理系统，以及制造基板的方法。