公开(公告)号：US06580036B2

公开(公告)日：2003-06-17

申请号：US09832193

申请日：2001-04-11

Applicant: Dock-Heung Kim ,  Yong-Il Kim

Inventor： Dock-Heung Kim ,  Yong-Il Kim

IPC: H01R1204

CPC classification number: H05K3/4652 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/0097 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913

Abstract: A multi-layer printed circuit board on which insulation resin layers and circuit pattern layers are alternatively stacked to form multiple layers, including: an insulation resin layer; a circuit pattern formed at the upper surface of the insulation resin layer; a blind via hole formed penetrating the insulation resin layer and the circuit pattern; a plated layer formed at the upper surface of the circuit pattern, at the inner wall face and the bottom of the blind via hole; an inner lead bump pad formed at the surface of the plated layer which is exposed to the lower surface of the insulation resin layer; and an outer lead bump pad formed on the circuit pattern which is formed at the upper surface of the insulation resin layer, whereby the problem of defective attachment of a bump due to a void present in a blind via hole is eliminated.

Abstract translation: 一种多层印刷电路板，其上绝缘树脂层和电路图案层交替堆叠形成多层，包括：绝缘树脂层; 形成在所述绝缘树脂层的上表面的电路图案; 穿过绝缘树脂层和电路图案的盲通孔; 在电路图案的上表面形成在盲通孔的内壁面和底部的镀层; 内部引线凸块焊盘，其形成在所述绝缘树脂层的下表面的所述镀层的表面， 以及形成在电路图案上的外部引线凸块焊盘，其形成在绝缘树脂层的上表面处，由此消除了由于存在于盲孔中的空隙而引起的凸起不良的附着问题。

公开(公告)号：US06555208B2

公开(公告)日：2003-04-29

申请号：US09891819

申请日：2001-06-26

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: B32B300

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

公开(公告)号：US20010038905A1

公开(公告)日：2001-11-08

申请号：US09891819

申请日：2001-06-26

Inventor： Masaru Takada ,  Hiroyuki Kobaryashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: B32B003/00

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。

公开(公告)号：US06183588B2

公开(公告)日：2001-02-06

申请号：US09460488

申请日：1999-12-14

Applicant: Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

Inventor： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B3100

CPC classification number: B32B43/00 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K3/007 ,  H05K3/025 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/467 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Abstract translation: 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

公开(公告)号：US6000130A

公开(公告)日：1999-12-14

申请号：US62816

申请日：1998-04-20

Applicant: Chi Shih Chang ,  Frank Daniel Egitto

Inventor： Chi Shih Chang ,  Frank Daniel Egitto

IPC: H01L23/50 ,  H01L23/538 ,  H05K1/11 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/462 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H05K1/113 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A self-supporting redistribution structure for directly mounting a semi-conductor chip to a multilayer electronic substrate is separately fabricated and then laminated to the multilayer substrate. The redistribution structure comprises a dielectric layer having plated vias communicating between its two major surfaces, redistribution lines and input/output pads on its upper major surface and joining patterns on its lower margin surface for electrical connection with the multilayer substrate. The metal plating in the plated vias of the redistribution device connects respective input/output pads on the upper surface of the redistribution structures with the joining patterns on its lower major surface. Input/output pads define an even (planar) topography with the redistribution lines to facilitate flip chip joining.

Abstract translation: 分别制造用于将半导体芯片直接安装到多层电子基板的自支撑再分布结构，然后层叠到多层基板。 再分布结构包括具有在其两个主表面之间连通的电镀通孔的电介质层，再分配线和其上主表面上的输入/输出焊盘，并且在其下边缘表面上连接图案以与多层基板电连接。 再分配装置的电镀通孔中的金属电镀将再分布结构的上表面上的相应输入/输出焊盘与其下主表面上的接合图案相连。 输入/输出焊盘用再分布线限定均匀（平面）形貌，以便于倒装芯片连接。

公开(公告)号：US3060076A

公开(公告)日：1962-10-23

申请号：US68729157

申请日：1957-09-30

Applicant: AUTOMATED CIRCUITS INC

Inventor： ROBINSON THOMAS L

IPC: H05K1/03 ,  H05K3/00 ,  H05K3/20 ,  H05K3/28 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4617 ,  H05K1/036 ,  H05K3/005 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/043 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2203/0108 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/1572 ,  Y10S425/811 ,  Y10T29/49126 ,  Y10T156/1056 ,  Y10T156/108

公开(公告)号：US20230164916A1

公开(公告)日：2023-05-25

申请号：US17834874

申请日：2022-06-07

Applicant: Celestica Technology Consultancy (Shanghai) Co. Ltd

Inventor： Jing LI ,  Haiju HUANG ,  Chenxia FENG ,  Chunmei WU

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/18 ,  H05K1/0298 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2203/02

Abstract: The present disclosure provides a printed circuit board and a wire arrangement method thereof. The printed circuit board includes a packaged chip and at least two connectors, wires of the packaged chip that are connected to different connectors are distributed on different board layers; and when the packaged chip is connected to one of the connectors, a via is backdrilled to form a high-speed path from the packaged chip to the connector, and copper walls of board layers corresponding to other connectors are drilled out. The wires of the packaged chip that are connected to different connectors are distributed on different board layers. When the packaged chip is connected to one of the connectors, according to backdrilling of different depths, the via is backdrilled to form a high-speed path from the packaged chip to the connector, and copper walls of board layers corresponding to other connectors are drilled out.

公开(公告)号：US11646127B2

公开(公告)日：2023-05-09

申请号：US16190266

申请日：2018-11-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroyuki Ohata

IPC: B32B27/00 ,  B32B37/00 ,  C08J3/00 ,  H01L23/00 ,  H05K3/00 ,  H01B3/30 ,  H01L23/14 ,  H01L23/498 ,  H05K3/46 ,  B32B27/08 ,  C08J3/12 ,  B32B37/24 ,  B32B37/06 ,  B32B37/10 ,  H05K1/18

CPC classification number: H01B3/307 ,  B32B27/08 ,  B32B37/06 ,  B32B37/10 ,  B32B37/24 ,  C08J3/12 ,  H01L23/145 ,  H01L23/49894 ,  H05K3/4632 ,  B32B2037/243 ,  B32B2250/24 ,  B32B2255/10 ,  B32B2305/55 ,  B32B2307/20 ,  B32B2307/206 ,  B32B2457/00 ,  B32B2457/08 ,  C08J2300/12 ,  H01L23/49822 ,  H05K1/185 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/10636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fibrillated liquid crystal polymer powder containing fibrillated liquid crystal polymer particles. A paste containing a dispersion medium and the fibrillated liquid crystal polymer powder. A method of producing the fibrillated liquid crystal polymer powder. A resin multilayer substrate obtained by laminating a plurality of resin sheets including at least one layer of a liquid crystal polymer sheet. On a surface of at least one layer of the liquid crystal polymer sheet, a thickness adjustment layer made of a fibrillated liquid crystal polymer powder containing fibrillated liquid crystal polymer particles is provided in a region insufficient in thickness when at least the plurality of resin sheets are laminated.

公开(公告)号：US20180242464A1

公开(公告)日：2018-08-23

申请号：US15756745

申请日：2016-08-08

Applicant: DENSO CORPORATION

Inventor： Kenichiro HASEGAWA ,  Tomohiro YOKOCHI ,  Yasunori KASAMA

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/0014 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/09454 ,  H05K2201/09527 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/09827

Abstract: Before a laminated body is subjected to hot pressing, at least two or more land electrodes are displaced from each other as viewed in the lamination direction, whereby at least two or more gaps disposed in the lamination direction are displaced from each other as viewed in the lamination direction. The hot pressing on the laminated body causes resin materials that compose resin films to flow and fill the gaps in the laminated body. Consequently, the planarity of a multilayer substrate can be improved to a greater extent than in a case where a plurality of gaps disposed in the lamination direction is located at the same position as viewed in the lamination direction.

公开(公告)号：US09812387B2

公开(公告)日：2017-11-07

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H05K3/36 ,  H05K3/00 ,  H05K3/22 ,  H05K3/40 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.