公开(公告)号：US20130127560A1

公开(公告)日：2013-05-23

申请号：US13739076

申请日：2013-01-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Shigeru Tago ,  Jun Sasaki ,  Satoshi Sasaki

IPC: H04B15/00 ,  H01P3/02

CPC classification number: H01P3/085 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01P1/20363 ,  H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/10 ,  H01P3/121 ,  H03H7/38 ,  H04B15/00 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/113 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: Unwanted radiation is reduced in a high-frequency signal transmission line that includes a ground conductor provided with an opening that overlaps a signal line. A dielectric element assembly has a relative dielectric constant ∈1 and has a first principal surface and a second principal surface. A signal line is provided in the dielectric element assembly. A ground conductor is provided in the dielectric element assembly and on the first principal surface side with respect to the signal line, faces the signal line, and is provided with an opening that overlaps the signal line. A high dielectric constant layer has a relative dielectric constant ∈2 higher than the relative dielectric constant ∈1 and is provided on the first principal surface so as to overlap the opening.

Abstract translation: 在包括具有与信号线重叠的开口的接地导体的高频信号传输线中减少了不需要的辐射。 电介质元件组件具有相对介电常数E1并且具有第一主表面和第二主表面。 信号线设置在电介质元件组件中。 接地导体设置在电介质元件组件中，并且相对于信号线在第一主表面侧面对信号线，并且设置有与信号线重叠的开口。 高介电常数层的相对介电常数E2高于相对介电常数E1，并且设置在第一主表面上以与开口重叠。

公开(公告)号：US08446556B2

公开(公告)日：2013-05-21

申请号：US13000615

申请日：2009-06-24

Applicant: Teruo Kawamura ,  Toshio Etoh

Inventor： Teruo Kawamura ,  Toshio Etoh

IPC: G02F1/1345

CPC classification number: H05K3/0052 ,  G02F1/13452 ,  H05K1/0268 ,  H05K1/118 ,  H05K2201/0394 ,  H05K2201/09727 ,  H05K2201/10681 ,  H05K2203/1545 ,  H05K2203/175

Abstract: Provided are a flexible printed circuit that reduces the chance of the occurrence of short-circuit failures caused by swarf generated from punching out flexible printed circuit, and an electric circuit structure having this flexible printed circuit and an electric circuit substrate to which the flexible printed circuit is connected. A flexible printed circuit (100) has a wiring pattern (2) formed on the flexible base film (1). The flexible printed circuit (100) is individually punched out to be separated in a condition where the wiring pattern (2) is disposed on the base film (1), and the wiring pattern (2) has a narrowed portion (2c) near the edge of the base film (1).

Abstract translation: 提供了一种柔性印刷电路，其减少了由冲出柔性印刷电路产生的切屑引起的短路故障的发生机会，以及具有该柔性印刷电路的电路结构和柔性印刷电路 已连接。 柔性印刷电路（100）具有形成在柔性基膜（1）上的布线图案（2）。 在布线图案（2）设置在基膜（1）上的状态下，柔性印刷电路（100）被单独冲压成分离，并且布线图案（2）具有靠近 底膜（1）的边缘。

公开(公告)号：US20130063902A1

公开(公告)日：2013-03-14

申请号：US13602612

申请日：2012-09-04

Applicant: Masato YOSHIDA ,  Tomohiro NAGAI ,  Hiroshi MATSUBARA

Inventor： Masato YOSHIDA ,  Tomohiro NAGAI ,  Hiroshi MATSUBARA

IPC: H05K7/00

CPC classification number: H05K1/0209 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0265 ,  H05K2201/0715 ,  H05K2201/09727

Abstract: A power supply control IC is mounted on a surface of a multilayer body that defines a power supply control circuit module. A first inner-layer electrode connecting an inductor element and a switching regulator element for the power supply control IC, another first inner-layer electrode connecting the inductor element and a capacitor element, and still another first inner-layer electrode connecting the switching regulator element and the capacitor element are located on upper layer regions of the multilayer body and are routed in between a mounting area of the power supply control IC and a peripheral wall of the multilayer body. The first inner-layer electrodes have widths that are wider than those of second inner-layer electrodes which are located near a center region of the multilayer body and transmit control signals.

Abstract translation: 电源控制IC安装在限定电源控制电路模块的多层体的表面上。 连接用于电源控制IC的电感器元件和开关调节器元件的第一内层电极，连接电感器元件和电容器元件的另一个第一内层电极和连接开关调节器元件的另一个第一内层电极 并且所述电容器元件位于所述多层体的上层区域，并且被布线在所述电源控制IC的安装区域和所述多层体的周壁之间。 第一内层电极具有比位于多层体的中心区附近的第二内层电极宽的宽度，并传输控制信号。

公开(公告)号：US08330365B2

公开(公告)日：2012-12-11

申请号：US12448755

申请日：2008-01-09

Applicant: Hyun-Sik Kim ,  Jung-Ho Park

Inventor： Hyun-Sik Kim ,  Jung-Ho Park

IPC: H01J17/49 ,  H01J17/34

CPC classification number: H01J9/02 ,  H01J2211/46 ,  H01J2217/49207 ,  H05K3/125 ,  H05K2201/09236 ,  H05K2201/09727 ,  H05K2203/013

Abstract: A method for formation of a line pattern using a multiple nozzle head includes forming a cell region in which display cells with a height corresponding to a multiple of a line gap of nozzles provided to the multiple nozzle head are repeated in two dimensions; and forming different kinds of first and second line patterns alternatively repeated on the cell region by ink-jet printing using the multiple nozzle head. When the multiple nozzle head scans once, the first and second line patterns are formed at the same time under the condition that the height of the display cells and a gap between two associative line patterns are a multiple of the line gap of nozzles. This method may improve productivity by reducing the number of scans of the multiple nozzle head, and also decrease the possibility of open circuit occurring when forming a line pattern by ink jetting.

Abstract translation: 使用多个喷嘴头形成线条图案的方法包括形成单元区域，其中具有对应于设置到多个喷嘴头的喷嘴的线间隙的倍数的高度的显示单元在二维中重复; 以及通过使用多个喷嘴头的喷墨打印在单元区域上形成不同种类的第一和第二线图案。 当多个喷嘴头扫描一次时，在显示单元的高度和两个相关线图案之间的间隙是喷嘴的线间隙的倍数的条件下，同时形成第一和第二线图案。 该方法可以通过减少多个喷嘴头的扫描次数来提高生产率，并且还通过喷墨形成线图案来降低开路发生的可能性。

公开(公告)号：US20120222891A1

公开(公告)日：2012-09-06

申请号：US13508974

申请日：2010-10-20

Applicant: Hisashi Ishida

Inventor： Hisashi Ishida

IPC: H05K1/03 ,  H05K3/10 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/0236 ,  H05K1/0233 ,  H05K1/141 ,  H05K2201/09727 ,  H05K2201/10265 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A first interconnect substrate includes a first conductor pattern. A second interconnect substrate includes a second conductor pattern. At least a portion of the second conductor pattern is formed in a region opposite the first conductor pattern. At least either the first conductor pattern or the second conductor pattern has a repeated structure. The first conductor pattern and the second conductor pattern constitute at least a portion of an electromagnetic band gap (EBG) structure.

Abstract translation: 第一互连基板包括第一导体图案。 第二互连基板包括第二导体图案。 第二导体图案的至少一部分形成在与第一导体图案相对的区域中。 第一导体图案或第二导体图案中的至少一个具有重复的结构。 第一导体图案和第二导体图案构成电磁带隙（EBG）结构的至少一部分。

公开(公告)号：US08253512B2

公开(公告)日：2012-08-28

申请号：US12781956

申请日：2010-05-18

Applicant: Guang-Feng Ou

Inventor： Guang-Feng Ou

IPC: H03H7/06

CPC classification number: H05K1/0233 ,  H05K1/167 ,  H05K2201/09727 ,  H05K2201/1006

Abstract: A low pass filter circuit includes an inductor and a capacitor. A first terminal of the inductor functions as an input to receive direct current voltage, and a second terminal of the inductor is connected to a first terminal of the capacitor through first and second conductor traces connected in series. A second terminal of the capacitor is grounded. Widths of the first and second conductor traces both range from about 2 mils to about 5 mils. A node between the first and second conductor traces outputs the direct current.

Abstract translation: 低通滤波器电路包括电感器和电容器。 电感器的第一端子用作接收直流电压的输入，并且电感器的第二端子通过串联连接的第一和第二导体迹线连接到电容器的第一端子。 电容器的第二个端子接地。 第一和第二导体迹线的宽度都在约2密耳至约5密耳的范围内。 第一和第二导体迹线之间的节点输出直流电流。

公开(公告)号：US20120200974A1

公开(公告)日：2012-08-09

申请号：US13362562

申请日：2012-01-31

Applicant: Yuuki Mikami ,  Toru Itabashi ,  Takahiko Furuta ,  Ryoichi Shiraishi ,  Yusuke Takahashi ,  Hiroaki Nakamura ,  Shigeki Nishiyama

Inventor： Yuuki Mikami ,  Toru Itabashi ,  Takahiko Furuta ,  Ryoichi Shiraishi ,  Yusuke Takahashi ,  Hiroaki Nakamura ,  Shigeki Nishiyama

IPC: H02H3/08 ,  H02H5/04

CPC classification number: H02H5/047 ,  H01H85/046 ,  H01H85/08 ,  H01H85/10 ,  H05K1/0265 ,  H05K1/0293 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10181

Abstract: An electronic control device includes a substrate, a plurality of component-mounted wires, a plurality of electronic components, a common wire, an interrupt wire and a protective layer. The component-mounted wires and the common wire are disposed on the substrate. The electronic components are mounted on the respective component-mounted wires and are coupled with the common wire. The interrupt wire is coupled between one component-mounted wire and the common wire, and is configured to melt in accordance with heat generated by an overcurrent to interrupt a coupling between the component-mounted wire and the common wire. The protective layer covers a surface of the substrate including the interrupt wire and defines an opening portion so that at least a portion of the interrupt wire is exposed.

Abstract translation: 电子控制装置包括基板，多个部件安装导线，多个电子部件，公共线，中断线和保护层。 组件安装线和公共线设置在基板上。 电子部件安装在相应的部件安装的导线上并与公共线耦合。 中断线耦合在一个部件安装的线和公共线之间，并且被配置为根据由过电流产生的热量熔化，以中断部件安装的线和公共线之间的耦合。 保护层覆盖包括中断线的基板的表面，并且限定开口部分，使得中断线的至少一部分被暴露。

公开(公告)号：US08238115B2

公开(公告)日：2012-08-07

申请号：US12824850

申请日：2010-06-28

Applicant: Yung-Chieh Chen ,  Cheng-Hsien Lee ,  Shou-Kuo Hsu ,  Shen-Chun Li ,  Hsien-Chuan Liang ,  Shin-Ting Yen

Inventor： Yung-Chieh Chen ,  Cheng-Hsien Lee ,  Shou-Kuo Hsu ,  Shen-Chun Li ,  Hsien-Chuan Liang ,  Shin-Ting Yen

IPC: H05K1/11 ,  H05K1/14 ,  G06F13/00

CPC classification number: H05K1/113 ,  G06F1/185 ,  H05K1/0251 ,  H05K2201/09409 ,  H05K2201/09727 ,  H05K2201/10159

Abstract: A computer motherboard includes a printed circuit board which includes a central processing unit (CPU) socket and a group of memory slots. The group of memory slots includes an in-line type memory slot and a surface mounted device (SMD) type memory slot. The in-line type memory slot includes a number of plated through holes. The SMD type memory slot is set between the in-line type memory slot and the CPU socket. The through holes of the in-line type memory slot are connected to the CPU socket through traces, pads of the SMD type memory slot are connected to corresponding through holes of the in-line type memory slot having the same pin definition.

Abstract translation: 计算机主板包括印刷电路板，其包括中央处理单元（CPU）插座和一组存储器插槽。 该组存储器插槽包括一个在线型存储器插槽和一个表面安装器件（SMD）型存储器插槽。 在线型存储槽包括多个电镀通孔。 SMD型内存插槽设置在串行型内存插槽和CPU插槽之间。 在线式存储插槽的通孔通过走线连接到CPU插座，SMD型存储插槽的焊盘连接到具有相同引脚定义的在线型存储器插槽的相应通孔。

公开(公告)号：US20120195008A1

公开(公告)日：2012-08-02

申请号：US13442801

申请日：2012-04-09

Applicant: Stephen R. MCCLURE ,  Joshua D. Banko ,  John P. Ternus

Inventor： Stephen R. MCCLURE ,  Joshua D. Banko ,  John P. Ternus

IPC: H05K1/00

CPC classification number: G06F1/1613 ,  G06F1/1626 ,  G06F1/1643 ,  G06F1/1656 ,  H04M1/0252 ,  H04M1/0266 ,  H04M1/0277 ,  H05K1/0281 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/09727 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49135 ,  Y10T29/4914 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A methodology for connecting device components with circuitry located at different levels and orientations relative to one another is described. First circuitry can be located on a multi-plane rigid circuit board where the multi-plane rigid circuit board can include at least one flexible member sharing a common substrate with the multi-plane rigid circuit board that extends from a body portion of the multi-plane rigid circuit board. The flexible member can include traces used to convey power and/or data and an interface coupled to the power and/or data traces. The flexible member can be deflected or twisted to connect first circuitry on the body portion of the multi-plane rigid circuit board to second circuitry associated with another device component.

Abstract translation: 描述了一种用于将设备组件与相对于彼此在不同级别和取向上的电路连接的方法。 第一电路可以位于多平面刚性电路板上，其中多平面刚性电路板可以包括至少一个与多平面刚性电路板共用公共衬底的柔性构件，该多平面刚性电路板从多层刚性电路板的主体部分延伸， 平面刚性电路板。 柔性构件可以包括用于传递功率和/或数据的迹线以及耦合到功率和/或数据迹线的接口。 柔性构件可以被偏转或扭曲以将多平面刚性电路板的主体部分上的第一电路连接到与另一个装置部件相关联的第二电路。

公开(公告)号：US20120182083A1

公开(公告)日：2012-07-19

申请号：US13431698

申请日：2012-03-27

Applicant: Masato KIKUCHI ,  Shunsuke MOCHIZUKI ,  Masahiro YOSHIOKA ,  Ryosuke ARAKI ,  Masaki HANDA ,  Takashi NAKANISHI ,  Hiroshi ICHIKI ,  Tetsujiro KONDO

Inventor： Masato KIKUCHI ,  Shunsuke MOCHIZUKI ,  Masahiro YOSHIOKA ,  Ryosuke ARAKI ,  Masaki HANDA ,  Takashi NAKANISHI ,  Hiroshi ICHIKI ,  Tetsujiro KONDO

IPC: H03H7/38

CPC classification number: H05K1/0243 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01P3/003 ,  H01P3/026 ,  H01P3/081 ,  H01P3/085 ,  H01P5/028 ,  H05K1/0248 ,  H05K3/32 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2203/1469 ,  H01L2924/00014

Abstract: A connection method includes the step of connecting, using a line on a dielectric element, two points through which a signal flows, the two points having different heights and the widths of the line at the positions of the two points having been adjusted on the basis of the thickness of the dielectric element.

Abstract translation: 连接方法包括以下步骤：使用电介质元件上的线连接信号流过的两个点，具有不同高度的两个点，并且在两个点的位置处的线的宽度已经基于 介电元件的厚度。