公开(公告)号：US20160353582A1

公开(公告)日：2016-12-01

申请号：US14848517

申请日：2015-09-09

Applicant: FuKui Precision Component (Shenzhen) Co., Ltd. ,  HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd. ,  Zhen Ding Technology Co., Ltd.

Inventor： WEI-SHUO SU

IPC: H05K3/24 ,  H05K3/06 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K3/244 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0154 ,  H05K2201/0338 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2203/0723 ,  H05K2203/1394

Abstract: The present disclosure relates to a method for manufacturing a printed circuit board. The method includes the steps as follows. First, a substrate including a base layer and a copper foil layer on a surface of the base layer is provided. Second, a conductive layer is formed on portions of the copper foil layer. Third, portions of the copper foil layer exposed from the conductive layer are removed by an etching process, and the conductive layer is thinner by the etching process. The reserved portions of the copper foil layer and the conductive layer forms a conductive pattern to obtain a printed circuit board without plating wires. A printed circuit board without plating wires made by the above method is also provided.

Abstract translation: 本公开涉及印刷电路板的制造方法。 该方法包括以下步骤。 首先，提供在基底层的表面上具有基底层和铜箔层的基板。 其次，在铜箔层的部分上形成导电层。 第三，通过蚀刻工艺去除从导电层露出的铜箔层的部分，并且通过蚀刻工艺使导电层更薄。 铜箔层和导电层的保留部分形成导电图案以获得没有电镀线的印刷电路板。 还提供了一种不用上述方法制成的电镀线的印刷电路板。

公开(公告)号：US09386706B2

公开(公告)日：2016-07-05

申请号：US14140803

申请日：2013-12-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sung Han ,  Young Do Kweon ,  Seung Min Baek ,  Yoon Su Kim ,  Young Jae Lee

IPC: H05K3/10

CPC classification number: H05K3/108 ,  H05K2201/098 ,  H05K2203/087 ,  H05K2203/092 ,  H05K2203/095 ,  H05K2203/1105 ,  H05K2203/111 ,  H05K2203/1184 ,  H05K2203/1383 ,  Y10T29/49155

Abstract: A printed circuit board includes an insulating layer; and a circuit pattern formed on the insulating layer. The circuit pattern includes a seed layer and a metal layer formed on the seed layer, and both sides of the seed layer are formed with an etched groove. Also, a method of manufacturing a printed circuit board includes: forming a seed layer on the insulating layer; forming a plating resist formed with an opening on the seed layer; forming a circuit pattern by performing plating processing on the opening; removing the plating resist; forming a passivation layer on the circuit pattern; performing dry etching on a remaining portion other than a side wall of the passivation layer; and performing wet etching the seed layer exposed on a surface by the dry etching.

Abstract translation: 印刷电路板包括绝缘层; 以及形成在绝缘层上的电路图案。 电路图案包括种子层和形成在种子层上的金属层，种子层的两侧形成有蚀刻槽。 另外，制造印刷电路板的方法包括：在绝缘层上形成晶种层; 在种子层上形成具有开口的电镀抗蚀剂; 通过在开口上进行电镀处理形成电路图案; 去除电镀抗蚀剂; 在电路图案上形成钝化层; 对钝化层的侧壁以外的剩余部分进行干蚀刻; 并且通过干蚀刻对表面上暴露的种子层进行湿法蚀刻。

公开(公告)号：US20160174374A1

公开(公告)日：2016-06-16

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K1/11 ,  H01L21/48 ,  H05K3/40 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

Abstract translation: 公开了一种在衬底中包括垂直沟槽布线的互连拓扑。 在一个实施例中，互连包括具有包括第一接地平面层的多个层的衬底; 形成差分信号对的一对信号导体，所述一对信号导体中的每个导体具有第一部分和第二部分，所述第二部分从所述第一部分延伸到所述多个层中的至少一个层中，其中， 第二部分小于第一部分的宽度; 并且其中所述第一接地层仅为第一部分层，并且具有比所述第一部分层更靠近所述一对信号导体的第一空隙区域。

公开(公告)号：US20160120040A1

公开(公告)日：2016-04-28

申请号：US14921868

申请日：2015-10-23

Applicant: Nascent Objects, Inc.

Inventor： Baback Elmieh ,  Saurabh Palan ,  Rex Wenters Crossen ,  Alexandre Jais

IPC: H05K3/46 ,  G05B19/4099 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

CPC classification number: H05K3/4679 ,  B29C33/0016 ,  B29C33/448 ,  B29C64/00 ,  B29C64/10 ,  B29C2043/3668 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y70/00 ,  G05B19/4099 ,  G05B2219/35134 ,  G05B2219/49007 ,  H05K1/0284 ,  H05K1/095 ,  H05K1/097 ,  H05K1/111 ,  H05K1/162 ,  H05K1/183 ,  H05K3/0005 ,  H05K3/0014 ,  H05K3/0044 ,  H05K3/0088 ,  H05K3/101 ,  H05K3/103 ,  H05K3/1258 ,  H05K3/26 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/0329 ,  H05K2201/098 ,  H05K2201/10265 ,  H05K2203/0126 ,  H05K2203/0228 ,  H05K2203/0292 ,  H05K2203/0514 ,  H05K2203/06 ,  H05K2203/0783 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1115 ,  H05K2203/1194 ,  H05K2203/128 ,  H05K2203/143 ,  H05K2203/163 ,  H05K2203/175 ,  H05K2203/302 ,  H05K2203/308

Abstract: A method for forming a three-dimensional object with at least one conductive trace comprises providing an intermediate structure that is generated (e.g., additively or subtractively generated) from a first material in accordance with a model design of the three-dimensional object. The intermediate structure may have at least one predefined location for the at least one conductive trace. The model design includes the at least one predefined location. Next, the at least one conductive trace may be generated adjacent to the at least one predefined location of the intermediate structure. The at least one conductive trace may be formed of a second material that has an electrical and/or thermal conductivity that is greater than the first material.

Abstract translation: 用至少一个导电迹线形成三维物体的方法包括提供根据三维物体的模型设计从第一材料产生（例如，相加地或相减地产生）的中间结构。 中间结构可以具有用于至少一个导电迹线的至少一个预定位置。 模型设计包括至少一个预定位置。 接下来，可以在中间结构的至少一个预定位置附近生成至少一个导电迹线。 所述至少一个导电迹线可以由具有大于第一材料的电和/或热导率的第二材料形成。

公开(公告)号：US20160007480A1

公开(公告)日：2016-01-07

申请号：US14856895

申请日：2015-09-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki Yosui

IPC: H05K3/30 ,  H05K1/02 ,  H01Q1/12 ,  H05K1/18

CPC classification number: H05K3/30 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01Q1/12 ,  H01Q1/2208 ,  H01Q1/2283 ,  H05K1/165 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/167

Abstract: A fabricating method according to the present disclosure is a component built-in multilayer substrate fabricating method for incorporating a component (12) in a resin multilayer substrate (11) formed by laminating and pressing thermoplastic resin sheets (111a to 111d) so as to crimp them to each other. With the fabricating method according to the present disclosure, a metal pattern (13) is provided on a component mounting surface of the thermoplastic resin sheet (111a). Further, the component (12) is inserted in the area sandwiched by the metal pattern (13). Out of widths relating to the area sandwiched by the metal pattern (13), the width in the component mounting surface side is assumed to be a width W2, and the width in the component-insertion side is assumed to be a width W3, the width W2 being equal to or larger than a width W1 of the component but less than the width W3.

Abstract translation: 根据本发明的制造方法是一种组件内置的多层基板的制造方法，用于将部件（12）并入到通过层压和压制热塑性树脂片（111a至111d）而形成的树脂多层基板（11）中以卷曲 他们彼此。 利用根据本公开的制造方法，在热塑性树脂片（111a）的部件安装表面上设置有金属图案（13）。 此外，将组件（12）插入夹在金属图案（13）的区域中。 在与由金属图案（13）夹着的区域相关的宽度之外，元件安装表面侧的宽度被假设为宽度W2，并且元件插入侧的宽度被假设为宽度W3， 宽度W2等于或大于部件的宽度W1但小于宽度W3。

公开(公告)号：US20150034366A1

公开(公告)日：2015-02-05

申请号：US14481188

申请日：2014-09-09

Applicant: Panasonic Corporation

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA ,  Hiromitsu TAKASHITA ,  Tsuyoshi TAKEDA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/119 ,  H01L2224/81385 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/0076 ,  H05K3/0079 ,  H05K3/0085 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0224 ,  H05K2201/0233 ,  H05K2201/0239 ,  H05K2201/0376 ,  H05K2201/0769 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09972 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/0143 ,  H05K2203/0228 ,  H05K2203/0264 ,  H05K2203/0285 ,  H05K2203/0565 ,  H05K2203/0706 ,  H05K2203/0776 ,  H05K2203/1163 ,  Y02P70/611

Abstract: One aspect of the present invention relates to a circuit board including an insulating base substrate; and a circuit layer that is formed of a conductor and that is provided on the surface of the insulating base substrate, wherein the insulating base substrate has a smooth surface having a surface roughness Ra of 0.5 μm or less, and the conductor is at least partially embedded in a wiring groove formed in the surface of the insulating base substrate.

Abstract translation: 本发明的一个方面涉及一种包括绝缘基底的电路板; 以及电路层，其由导体形成，并且设置在所述绝缘基底基板的表面上，其中所述绝缘基底具有表面粗糙度Ra为0.5μm以下的平滑表面，并且所述导体至少部分地 嵌入形成在绝缘性基板的表面的布线槽。

公开(公告)号：US20150027757A1

公开(公告)日：2015-01-29

申请号：US14074372

申请日：2013-11-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yee Na SHIN ,  Seung Eun Lee

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K3/4605 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/185 ,  H05K3/107 ,  H05K3/426 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2201/098 ,  H01L2924/00

Abstract: Disclosed herein is a printed circuit board (PCB) including a glass core for maintaining sufficient rigidity while maintaining a thin thickness to minimize warpage. The PCB includes a glass core having upper and lower surfaces in which pattern formation grooves and through via holes are formed, a plating layer filled in the pattern formation groves and the through via holes, insulating layers stacked on the upper and lower surfaces of the glass core, and solder resist layers formed on the insulating layers via coating.

Abstract translation: 本文公开了一种印刷电路板（PCB），其包括玻璃芯，用于保持足够的刚度，同时保持薄的厚度以使翘曲最小化。 PCB包括具有上表面和下表面的玻璃芯，其中形成图案形成沟槽和穿过通孔，填充在图案形成沟槽中的镀层和穿通通孔，堆叠在玻璃的上表面和下表面上的绝缘层 芯和阻焊层，通过涂层形成在绝缘层上。

公开(公告)号：US20140218909A1

公开(公告)日：2014-08-07

申请号：US14133822

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ariyoshi TETSUO ,  Cheon Ho PARK ,  Jong Pil WON ,  Ji Hoon YUN ,  Jun Ho JUNG

IPC: F21K99/00 ,  H01L33/58 ,  H01L27/15

CPC classification number: F21K9/64 ,  F21K9/27 ,  F21K9/65 ,  F21K9/69 ,  F21V5/02 ,  F21V5/043 ,  F21Y2101/00 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L33/38 ,  H01L33/44 ,  H01L2224/13 ,  H01L2224/48091 ,  H05K1/021 ,  H05K1/0256 ,  H05K1/189 ,  H05K3/107 ,  H05K3/305 ,  H05K3/44 ,  H05K2201/0338 ,  H05K2201/0358 ,  H05K2201/0376 ,  H05K2201/09154 ,  H05K2201/098 ,  H05K2201/10106 ,  H05K2203/0139 ,  H05K2203/025 ,  H01L2924/00014

Abstract: A light source module including a substrate, a plurality of light emitting devices installed on the substrate, and a plurality of lenses installed on the substrate to cover the plurality of light emitting devices, respectively, and each of the plurality of lenses having a pair of open end portions facing one another, the plurality of lenses arranged such that an open end portion of one lens faces an opened end portion of an adjacent lens is provided.

Abstract translation: 一种光源模块，包括基板，安装在基板上的多个发光装置，以及分别安装在基板上以覆盖多个发光装置的多个透镜，并且多个透镜中的每一个具有一对 所述多个透镜被设置为使得一个透镜的开口端部面向相邻透镜的开口端部。

公开(公告)号：US20140160370A1

公开(公告)日：2014-06-12

申请号：US14090404

申请日：2013-11-26

Applicant: Samsung Corning Precision Materials Co., Ltd.

Inventor： Jae Hong Lee ,  Jin Soo An ,  Jung Hong Oh ,  Chang Moog Rim

IPC: H05K1/02 ,  G06F1/16

CPC classification number: H05K3/064 ,  G06F3/041 ,  G06F2203/04103 ,  H05K2201/0326 ,  H05K2201/098 ,  H05K2201/10053 ,  H05K2201/10128

Abstract: A transparent conductive substrate that is used for detecting a touched position on a touch screen panel (TSP), and a touch panel including the same. The transparent conductive substrate includes a base substrate and a transparent conductive layer formed on the base substrate. The transparent conductive layer includes a patterned area which is provided by coating the base substrate with a transparent conductive film containing indium tin oxide and a non-patterned area through which the base substrate is exposed. The thickness of the transparent conductive layer ranges from 110 to 180 nm.

Abstract translation: 用于检测触摸屏面板（TSP）上的触摸位置的透明导电基板和包括该透明导电基板的触摸面板。 透明导电基板包括基底基板和形成在基底基板上的透明导电层。 透明导电层包括图案化区域，其通过用含有氧化铟锡的透明导电膜和暴露基底基板的非图案化区域涂覆基底基板而提供。 透明导电层的厚度为110〜180nm。

公开(公告)号：US08434222B2

公开(公告)日：2013-05-07

申请号：US12870072

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/0296 ,  C25D5/022 ,  C25D5/10 ,  C25D7/00 ,  H05K1/0245 ,  H05K3/18 ,  H05K3/184 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract translation: 具有第一适应性掩模部分的第一艺术品层允许渐变量的光进入下面的第一光致抗蚀剂层。 在显影第一光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于产生圆形迹线的至少下部。 电介质层层叠在下部，具有第二可适应掩模部分的第二艺术品层允许渐变量的光通过第二光致抗蚀剂层。 在显影第二光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于至少形成圆形迹线的上部。 去除光致抗蚀剂和介电层，导致具有圆形差分对迹线的电路设备。