公开(公告)号：US20060108680A1

公开(公告)日：2006-05-25

申请号：US11285334

申请日：2005-11-22

Applicant: Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

Inventor： Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

IPC: H01L23/04 ,  H05K7/06

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09836

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract translation: 多层印刷电路板（PCB）包括第一布线层，第一布线层之上的中间层，中间层上方的第二布线层和形成在中间层和第二布线层中的倾斜孔。 该制造方法包括以下步骤：在第一布线层上形成第一布线层并形成第一布线，在第一布线层上形成中间层，在中间层上形成第二布线层，在中间层形成倾斜孔 层和第二线层，其中倾斜通孔的方向不与第一和第二线层正交，通过蚀刻方法在第二线层上形成第二布线，并且在通孔中形成电镀层以连接 第一布线和第二布线。

公开(公告)号：US07024763B2

公开(公告)日：2006-04-11

申请号：US10723269

申请日：2003-11-26

Applicant: Gaetan L. Mathieu ,  Igor Y. Khandros ,  Carl Reynolds

Inventor： Gaetan L. Mathieu ,  Igor Y. Khandros ,  Carl Reynolds

IPC: H05K3/30

CPC classification number: H05K3/42 ,  G01R1/06711 ,  G01R1/07307 ,  G01R3/00 ,  H05K3/308 ,  H05K2201/09836 ,  H05K2203/0338 ,  Y10T29/49117 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49194

Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

公开(公告)号：US07011988B2

公开(公告)日：2006-03-14

申请号：US11145948

申请日：2005-06-07

Applicant: Robert Forcier

Inventor： Robert Forcier

IPC: H01L21/44

CPC classification number: H05K1/185 ,  B81C1/0023 ,  G02B6/43 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/02333 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/186 ,  H05K2201/09836 ,  H05K2203/061 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512

Abstract: A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

Abstract translation: 用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。 芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在 组件。 第一电介质层优选地放置在部件上，从而将部件嵌入结构中。 通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。 使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。 多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

公开(公告)号：US20050087356A1

公开(公告)日：2005-04-28

申请号：US10704131

申请日：2003-11-10

Applicant: Robert Forcier

Inventor： Robert Forcier

IPC: B81B7/00 ,  B81B7/02 ,  G02B6/43 ,  H01L21/60 ,  H01L23/31 ,  H01L23/433 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/02

CPC classification number: H05K1/185 ,  B81C1/0023 ,  G02B6/43 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/02333 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/186 ,  H05K2201/09836 ,  H05K2203/061 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512

Abstract: A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

Abstract translation: 用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。 芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在 组件。 第一电介质层优选地放置在部件上，从而将部件嵌入结构中。 通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。 使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。 多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

公开(公告)号：US20040201396A1

公开(公告)日：2004-10-14

申请号：US10832845

申请日：2004-04-27

Inventor： Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs JR.

IPC: G01R031/26

CPC classification number: H01R12/52 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/57 ,  H01R13/2414 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1061 ,  H05K13/0465 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

公开(公告)号：US06774486B2

公开(公告)日：2004-08-10

申请号：US09974947

申请日：2001-10-10

Applicant: Larry D. Kinsman

Inventor： Larry D. Kinsman

IPC: H01L2348

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

公开(公告)号：US06774315B1

公开(公告)日：2004-08-10

申请号：US09577457

申请日：2000-05-24

Applicant: Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

Inventor： Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

IPC: H01R1214

CPC classification number: H01R12/52 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/57 ,  H01R13/2414 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1061 ,  H05K13/0465 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract translation: 用于将芯片裸片直接连接到电路卡而不封装的单个低模量材料的柔性兼容层。 灵活的柔性层提供了芯片和电路卡中CTE热失配引起的应力消除。 在所述顺应层中形成镀铜通孔的阵列，每个通孔终止于铜衬垫的相对表面上。 而不是铜，也可以使用其他金属，例如金或镍。 一组孔可以位于所述通孔阵列之间以提供额外的弹性。 电镀通孔可以相对于所述相对的表面成角度，以允许额外的垂直和水平应力释放。 将一个表面上的焊盘与芯片模具上的高熔点C-4焊球或柱的连接导致焊料填充的通孔。 将另一个表面上的焊盘的低熔点焊接连接到电路卡允许卡的非破坏性返修。

公开(公告)号：US20030146510A1

公开(公告)日：2003-08-07

申请号：US10293564

申请日：2002-11-14

Inventor： Ray Chien

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48 ,  H01L021/50 ,  H01L021/48 ,  H01L021/44

CPC classification number: H05K3/4038 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2203/0235 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/00

Abstract: An elastomer interposer employed between a package and a printed circuit board and the method of manufacturing the same are disclosed. The elastomer interposer includes an elastomer, a plurality of conductive wires, Cu pads, solder resistant blocks and Ni/Au plated pads. The elastomer has two contact surfaces. The conductive wires are arranged inside the elastomer at a certain interval and tilted toward one of the contact surfaces with an inclined angle. The Cu pads are formed on both of the surfaces at a space, and electrically connected to the corresponding conductive wires. Also, the Ni/Au plated pads are formed over the Cu pads.

Abstract translation: 公开了一种在封装和印刷电路板之间采用的弹性体插入件及其制造方法。 弹性体插入件包括弹性体，多根导线，铜焊盘，阻焊块和Ni / Au电镀垫。 弹性体具有两个接触表面。 导线以一定的间隔配置在弹性体的内侧，以倾斜角朝向其中一个接触面倾斜。 Cu焊盘在空间的两个表面上形成，并且电连接到相应的导线。 此外，Ni / Au电镀焊盘形成在Cu焊盘上。

公开(公告)号：US5513430A

公开(公告)日：1996-05-07

申请号：US293365

申请日：1994-08-19

Applicant: Arnold W. Yanof ,  William Dauksher

Inventor： Arnold W. Yanof ,  William Dauksher

IPC: G01R3/00 ,  H05K3/40 ,  H05K3/02

CPC classification number: H05K3/4007 ,  G01R3/00 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2203/0542 ,  H05K2203/0577 ,  Y10T29/49155

Abstract: A probe card (40, 55) having probe card probes (36, 56) and a method for fabricating the probe card probes (36, 56). A layer of resist (23) is formed on a plating base (21). The layer of resist (23) is exposed to radiation (32) and developed to provide angled, tapered openings (33) exposing portions of the plating base (22). An electrically conductive material is electroplated on the exposed portions of the plating base (22) and fills the angled, tapered openings (33). The layer of resist (23) and portions of the plating base (22) between the electroplated conductive material are removed. The electrically conductive material forms the probe card probes (36) which are angled and tapered. In addition, the compliant probe card probes (56) may be stair-step shaped.

Abstract translation: 具有探针卡探针（36,56）的探针卡（40,55）和用于制造探针卡探针（36,56）的方法。 在电镀基体（21）上形成有抗蚀剂层（23）。 抗蚀剂层（23）暴露于辐射（32）并显影以提供倾斜的锥形开口（33），暴露电镀基底（22）的部分。 导电材料电镀在电镀基座（22）的露出部分上并填充有角度的锥形开口（33）。 去除了电镀层（23）和电镀基底（22）在电镀导电材料之间的部分。 导电材料形成了成角度和锥形的探针卡探头（36）。 此外，兼容的探针卡探针（56）可以是台阶形状。

公开(公告)号：US5436062A

公开(公告)日：1995-07-25

申请号：US193191

申请日：1994-02-14

Applicant: Walter Schmidt ,  Marco Martinelli

Inventor： Walter Schmidt ,  Marco Martinelli

IPC: H05K1/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  B32B3/00 ,  C23F1/02

CPC classification number: H05K3/4655 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/4635 ,  H05K3/4641 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  Y10S428/901 ,  Y10T428/24917

Abstract: In a metal-clad laminate the requirements concerning the mechanical strength are functionally separated from the circuit connection requirement, so as to be able to bring the circuit connection, particularly for signals, "closer" to the electrotechnical characteristics of the chips. For this purpose and without taking account of the mechanical strength of the substrate, the layout miniaturization is optimized. In place of a circuit board (MCM), a laminate which can be built up to a circuit board is produced. The inventive laminate comprises an extremely thin foil with a plurality of extremely small holes simultaneously etched in an etching process. The hole diameter can be reduced by almost an order of magnitude (up to 20 .mu.m), which permits a sub-100 .mu.m technology. Such a laminate is not used as a mechanical support and is only provided for signal guidance. The effect of the miniaturization can be seen in the diameter for the plated-through holes. With a hole diameter reduction there is an increase in the current path density, which gives over 10000 plated-through holes per dm.sup.2. A drawing shows the compression ratio compared with standard technology.

Abstract translation: PCT No.PCT / CH93 / 00145 Sec。 371日期1994年2月14日 102（e）1994年2月14日PCT PCT 1993年6月9日PCT公布。 公开号WO93 / 26143 日期为1993年12月23日。在覆金属层压板中，关于机械强度的要求在功能上与电路连接要求分离，以便能够使电路连接，特别是对于信号，“更接近”电工特性 的芯片。 为此，不考虑基板的机械强度，优化了布局小型化。 代替电路板（MCM），可以生产可构建到电路板的层压板。 本发明的层压板包括在蚀刻工艺中同时蚀刻的具有多个极小孔的极薄箔。 孔径可以减少几乎一个数量级（高达20微米），这允许小于100微米的技术。 这种层压体不用作机械支撑，并且仅用于信号引导。 电镀通孔的直径可以看出小型化的效果。 随着孔径减小，电流通道密度增加，每dm2提供超过10000个电镀通孔。 图表显示了与标准技术相比的压缩比。