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81.发明申请公开(公告)号：US20180096726A1
公开(公告)日：2018-04-05
申请号：US15706342
申请日：2017-09-15
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
IPC: G11C13/00
CPC classification number: G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号：US20180074218A1
公开(公告)日：2018-03-15
申请号：US15552012
申请日：2016-02-12
Applicant: UNITY SEMICONDUCTOR
Inventor： Gerd REIME
IPC: G01V3/08
CPC classification number: G01V3/088
Abstract: The invention relates to a method and a measuring arrangement for detecting an object (3) hidden behind an article (1). The method comprises the following steps: applying a first alternating voltage (5) to a first sensor (7); applying a second alternating voltage (9) to a second sensor (11) arranged adjacent to the first sensor (7); determining an effect (15) of the article (1) on at least one of the alternating voltages (5, 9) depending on a distance (13) of the sensor (7, 11) to the article (1); determining a change (17) in the dependent effect (15) occurring during a movement (19) of the sensor (7, 11) along the article (1); and detecting the object (3) in accordance with the change (17) of the dependent effect (15). In this way, a detection of an object hidden behind an article is improved such that the object can be recognized as independently as possible from a relative position of the device to the article, in particular, an angular position, in particular also if the device for detecting the object is manually moved beyond the article.
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公开(公告)号：US09857313B2
公开(公告)日：2018-01-02
申请号：US15515227
申请日：2015-09-29
Applicant: UNITY SEMICONDUCTOR
Inventor： Mayeul Durand De Gevigney , Philippe Gastaldo
CPC classification number: G01N21/9505 , G01B11/2441 , G01M11/331 , G01N21/8806 , G01N21/8851 , G01N21/9501 , G01N21/9503 , G01N2021/8874
Abstract: A method for inspecting a wafer, includes: rotating the wafer about an axis of the wafer, emitting from a light source, two pairs of incident coherent light beams, each pair forming, at the intersection between the two beams, a measurement volume, a portion of the main wafer surface passing through each of the measurement volumes during the rotation, collecting a light beam scattered by the wafer surface, capturing the collected light and emitting an electrical signal representing the variation in the collected light intensity, detecting in the signal, a frequency, being the time signature of a defect through a respective measurement volume, for each detected signature, determining a visibility parameter, on the basis of the visibility determined, obtaining an item of information on the size of the defect, and cross-checking the items of information to determine the size of the defect.
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公开(公告)号：US09837149B2
公开(公告)日：2017-12-05
申请号：US15181009
申请日：2016-06-13
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Bruce Lynn Bateman , Christophe Chevallier , Darrell Rinerson , Chang Hua Siau
CPC classification number: G11C13/004 , G11C7/12 , G11C7/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , G11C2213/77
Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
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公开(公告)号：US09831425B2
公开(公告)日：2017-11-28
申请号：US14844805
申请日：2015-09-03
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, Jr. , Lawrence Schloss , Philip Swab , Edmond Ward
CPC classification number: H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
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Patent Agency Ranking
公开(公告)号：US09767899B2
公开(公告)日：2017-09-19
申请号：US15366293
申请日：2016-12-01
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
Abstract: A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a disturb isolator circuit operatively coupled to the MEs to compensate for disturbances of a magnitude of a signal associated with a selected two-terminal resistive memory element in the array.
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公开(公告)号：US09711212B2
公开(公告)日：2017-07-18
申请号：US15090216
申请日：2016-04-04
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
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公开(公告)号：US20170033158A1
公开(公告)日：2017-02-02
申请号：US15231331
申请日：2016-08-08
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Lidia Vereen , Bruce L. Bateman , David A. Eggleston , Louis C. Parrillo
IPC: H01L27/24 , H01L23/528 , H01L45/00
CPC classification number: H01L27/249 , H01L23/528 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1616
Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
Abstract translation: 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的水平线对之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。
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89.发明授权Preservation circuit and methods to maintain values representing data in one or more layers of memory 有权保存电路和保持在一层或多层存储器中表示数据的值的方法公开(公告)号：US09536607B2
公开(公告)日：2017-01-03
申请号：US14727190
申请日：2015-06-01
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Robert Norman
CPC classification number: G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。
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公开(公告)号：US20160322104A1
公开(公告)日：2016-11-03
申请号：US15205882
申请日：2016-07-08
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Chang Hua Siau , Bruce Lynn Bateman
IPC: G11C13/00
CPC classification number: G11C5/06 , G11C5/08 , G11C7/00 , G11C7/04 , G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/24 , G11C2213/71
Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.
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