公开(公告)号：US20200020523A1

公开(公告)日：2020-01-16

申请号：US16507821

申请日：2019-07-10

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/02

Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.

公开(公告)号：US10290506B2

公开(公告)日：2019-05-14

申请号：US15431049

申请日：2017-02-13

Applicant: Tokyo Electron Limited

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/28 ,  H01L29/51 ,  H01L21/67 ,  H01L21/683 ,  H01J37/32

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

公开(公告)号：US09899219B2

公开(公告)日：2018-02-20

申请号：US15232330

申请日：2016-08-09

Applicant: Tokyo Electron Limited

Inventor： Vinh Luong ,  Akiteru Ko

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/683 ,  H01L21/66 ,  H01L21/67

CPC classification number: H01L21/0337 ,  G03F7/0043 ,  G03F7/094 ,  G03F7/405 ,  H01J2237/3342 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/32139 ,  H01L21/67017 ,  H01L21/67109 ,  H01L21/6831 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: Provided is a method of trimming an inorganic resist in an integration scheme, the method comprising: disposing a substrate in a process chamber, the substrate having an inorganic resist layer and an underlying layer comprising an oxide layer, a silicon nitride layer, and a base layer, the inorganic resist layer having an inorganic structure pattern; performing an inorganic resist trimming process to selectively remove a portion of the inorganic resist structure pattern on the substrate, the trimming process using a first etchant gas mixture and generating a first pattern; controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives; wherein the first etchant gas mixture comprises a fluorine-containing gas and a diluent gas; and wherein the target integration objectives include a target critical dimension (CD), a target line edge roughness (LER), a target line width roughness (LWR) and a target substrate throughput.

公开(公告)号：US20170358450A1

公开(公告)日：2017-12-14

申请号：US15491432

申请日：2017-04-19

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko ,  Angelique Raley ,  Sophie Thibaut ,  Satoru Nakamura ,  Nihar Mohanty

IPC: H01L21/033 ,  H01L21/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31138 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: Provide is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a post spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the exposing the patterned structure, the atomic layer conformal deposition process, and the post spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

公开(公告)号：US09812325B2

公开(公告)日：2017-11-07

申请号：US15255863

申请日：2016-09-02

Applicant: Tokyo Electron Limited

Inventor： Nihar Mohanty ,  Akiteru Ko

IPC: H01L21/033 ,  B81C1/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/0337 ,  B81C1/00404 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  Y10S438/947

Abstract: Techniques herein provide a process to reform or flatten asymmetric spacers to form a square profile which creates symmetric spacers for accurate pattern transfer. Initial spacer formation typically results in spacer profiles with a curved or sloped top surfaces. This asymmetric top surface is isolated while protecting a remaining lower portion of the spacer. The top surface is removed using a plasma processing step resulting in spacers having a squared profile that enables further patterning and/or accurate pattern transfer.

公开(公告)号：US09786503B2

公开(公告)日：2017-10-10

申请号：US15089961

申请日：2016-04-04

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Nihar Mohanty ,  Akiteru Ko

IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/02186 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.

公开(公告)号：US20170207103A1

公开(公告)日：2017-07-20

申请号：US15405977

申请日：2017-01-13

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Elliott Franke ,  Akiteru Ko ,  Aelan Mosden

IPC: H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/32135 ,  H01L21/0337 ,  H01L21/67109

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon selected from the group consisting of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), and doped silicon that fills a trench or via within a retention layer, and selectively removing at least a portion of the target layer from the retention layer. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

公开(公告)号：US20170069495A1

公开(公告)日：2017-03-09

申请号：US15255863

申请日：2016-09-02

Applicant: Tokyo Electron Limited

Inventor： Nihar Mohanty ,  Akiteru Ko

IPC: H01L21/033 ,  H01L21/3065

CPC classification number: H01L21/0337 ,  B81C1/00404 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  Y10S438/947

Abstract: Techniques herein provide a process to reform or flatten asymmetric spacers to form a square profile which creates symmetric spacers for accurate pattern transfer. Initial spacer formation typically results in spacer profiles with a curved or sloped top surfaces. This asymmetric top surface is isolated while protecting a remaining lower portion of the spacer. The top surface is removed using a plasma processing step resulting in spacers having a squared profile that enables further patterning and/or accurate pattern transfer.

Abstract translation: 本文的技术提供了改造或平坦化不对称间隔物以形成方形轮廓的方法，其形成用于精确图案转印的对称间隔物。 初始间隔物形成通常导致具有弯曲或倾斜的顶表面的间隔物分布。 隔离该非对称顶表面，同时保护间隔物的剩余下部。 使用等离子体处理步骤去除顶部表面，得到具有能够进一步图案化和/或精确图案转印的平面轮廓的间隔物。

公开(公告)号：US09576812B2

公开(公告)日：2017-02-21

申请号：US15085186

申请日：2016-03-30

Applicant: Tokyo Electron Limited

Inventor： Elliott Franke ,  Vinayak Rastogi ,  Akiteru Ko ,  Kiyohito Ito

IPC: H01L21/311 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/308 ,  H01L21/67

CPC classification number: H01L21/30655 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/67069

Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

Abstract translation: 提供了使用刻面和钝化层在基底上产生结构轮廓的方法。 执行产生刻面侧壁和期望拐点的第一等离子体蚀刻工艺; 使用氧，氮或组合的氧和氮等离子体进行第二等离子体蚀刻工艺，产生钝化层; 以及使用刻蚀侧壁和钝化层上的蚀刻化学品的操作变量的第三等离子体蚀刻工艺，以诱导差分蚀刻速率以在结构的近水平表面上实现突破，其中所用的第三等离子体蚀刻被配置为产生 基板上的目标侧壁轮廓直到底层停止层。 在第一等离子体蚀刻工艺，第二等离子体蚀刻工艺和/或第三等离子体蚀刻工艺的性能中控制所选择的两个或更多个等离子蚀刻变量，以实现目标侧壁轮廓目标。

公开(公告)号：US20160023238A1

公开(公告)日：2016-01-28

申请号：US14340721

申请日：2014-07-25

Applicant: Tokyo Electron Limited

Inventor： Nihar Mohanty ,  Akiteru Ko ,  Chi-Chun Liu

IPC: B05D1/32 ,  B05D3/02 ,  B05D1/00 ,  B05D3/06 ,  H01J37/32

CPC classification number: H01J37/32091 ,  B81C1/00428 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31058

Abstract: Techniques herein include methods for curing a layer of material (such as a resist) on a substrate to enable relatively greater heat reflow resistance. Increasing reflow resistance enables successful directed self-assembly of block copolymers. Techniques include receiving a substrate having a patterned photoresist layer and positioning this substrate in a processing chamber of a capacitively coupled plasma system. The patterned photoresist layer is treated with a flux of electrons by coupling negative polarity direct current power to a top electrode of the plasma processing system during plasma processing. The flux of electrons is accelerated from the top electrode with sufficient energy to pass through a plasma and its sheath, and strike the substrate such that the patterned photoresist layer changes in physical properties, which can include an increased glass-liquid transition temperature.

Abstract translation: 本文的技术包括用于固化衬底上的材料层（例如抗蚀剂）的方法，以使得能够相对更大的耐热回流性。 增加回流电阻使嵌段共聚物成功引导自组装。 技术包括接收具有图案化光致抗蚀剂层的衬底并将该衬底定位在电容耦合等离子体系统的处理室中。 通过在等离子体处理期间将负极性直流电力耦合到等离子体处理系统的顶部电极，用电子束来处理图案化的光致抗蚀剂层。 电子通量从顶部电极以足够的能量被加速以通过等离子体及其鞘，并撞击基板，使得图案化的光致抗蚀剂层的物理性质发生变化，这可能包括玻璃 - 液体转变温度升高。