公开(公告)号：US20170330729A1

公开(公告)日：2017-11-16

申请号：US15667951

申请日：2017-08-03

Applicant: Reno Technologies, Inc.

Inventor： Anton Mavretic

IPC: H01J37/32 ,  H01L29/778 ,  H01L21/02 ,  H01L21/3065 ,  H04B1/44 ,  H03H7/38

CPC classification number: H01J37/32082 ,  H01J2237/334 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L28/20 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/861 ,  H02M3/33569 ,  H03H7/38 ,  H03H7/40 ,  H03K17/102 ,  H03K17/687 ,  H03K17/691 ,  H03K17/7955 ,  H03K2017/6875 ,  H04B1/44

Abstract: In one embodiment, a switching circuit includes a first switch coupled to a first switch terminal, the first switch comprising at least one gallium nitride high-electron mobility transistor (GaN HEMT); a second switch coupled in series with the first switch and a second switch terminal, the second switching comprising a GaN HEMT; and at least one power source configured to provide power to the first switch and the second switch; wherein the second switch is configured to drive the first switch ON and OFF.

公开(公告)号：US20170323785A1

公开(公告)日：2017-11-09

申请号：US15279314

申请日：2016-09-28

Applicant: Lam Research Corporation

Inventor： Akhil Singhal ,  Joseph Hung-chi Wei ,  Yisha Mao ,  Bart J. van Schravendijk

IPC: H01L21/02 ,  H01L43/08 ,  H01L43/02 ,  C23C16/50 ,  C23C16/24 ,  C23C16/455 ,  H01J37/32 ,  H01L43/12

CPC classification number: H01L21/02274 ,  C23C16/325 ,  C23C16/345 ,  C23C16/50 ,  C23C16/515 ,  C23C16/56 ,  H01J37/32009 ,  H01J37/32082 ,  H01J37/32155 ,  H01J37/32165 ,  H01J37/3244 ,  H01J2237/3321 ,  H01J2237/334 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/56 ,  H01L23/291 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Methods of depositing conformal, dense silicon-containing films having low hydrogen content are provided herein. Methods involve pulsing a plasma while exposing a substrate to a silicon-containing precursor and reactant to facilitate a primarily radical-based pulsed plasma enhanced chemical vapor deposition process for depositing a conformal silicon-containing film. Methods also involve periodically performing a post-treatment operation whereby, for every about 20 Å to about 50 Å of film deposited using pulsed plasma PECVD, the deposited film is exposed to an inert plasma to densify and reduce hydrogen content in the deposited film.

公开(公告)号：US09812294B2

公开(公告)日：2017-11-07

申请号：US15172004

申请日：2016-06-02

Applicant: Lam Research Corporation

Inventor： John C. Valcore, Jr. ,  Harmeet Singh ,  Bradford J. Lyndaker

IPC: H01J37/32 ,  H05H1/24 ,  H03L7/00 ,  H03K3/01 ,  H03L7/06 ,  H05H1/46

CPC classification number: H01J37/32146 ,  H01J37/32082 ,  H01J37/32174 ,  H01J37/32183 ,  H01J37/3244 ,  H01J37/3255 ,  H01J2237/327 ,  H03K3/01 ,  H03L7/00 ,  H03L7/06 ,  H05H2001/4682

Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

公开(公告)号：US09799531B2

公开(公告)日：2017-10-24

申请号：US15195449

申请日：2016-06-28

Applicant: Applied Materials, Inc.

Inventor： Swaminathan T. Srinivasan ,  Fareen Adeni Khaja ,  Errol Antonio C. Sanchez ,  Patrick M. Martin

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01J37/32

CPC classification number: H01L21/02658 ,  H01J37/32082 ,  H01J37/32422 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31116 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/267 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

公开(公告)号：US20170271194A1

公开(公告)日：2017-09-21

申请号：US15427590

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU

IPC: H01L21/687 ,  H01L21/67 ,  H01J37/32 ,  H01L21/3065

CPC classification number: H01L21/68785 ,  H01J37/32082 ,  H01J37/32715 ,  H01J37/32724 ,  H01J37/32935 ,  H01J37/3299 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67248 ,  H01L21/67259 ,  H01L21/67288 ,  H01L21/6831 ,  H01L21/68742

Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.

公开(公告)号：US20170263450A1

公开(公告)日：2017-09-14

申请号：US15609864

申请日：2017-05-31

Applicant: Lam Research Corporation

Inventor： Shankar Swaminathan ,  Frank L. Pasquale ,  Adrien LaVoie

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/40 ,  C23C16/455 ,  H01J37/32 ,  H01L21/31 ,  H01L21/67 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L21/02186 ,  C23C16/045 ,  C23C16/405 ,  C23C16/45542 ,  H01J37/32082 ,  H01J37/32192 ,  H01J37/32449 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31 ,  H01L21/3141 ,  H01L21/67005 ,  H01L27/222 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/06 ,  H01L45/12 ,  H01L45/141 ,  H01L45/16

Abstract: The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO2) layer deposited through an atomic layer deposition reaction. In some embodiments, the encapsulation layer may be deposited as a bilayer, with an electrically favorable layer formed atop a protective layer. In certain implementations, gaps between neighboring memory stacks may be filled with titanium oxide, for example through an atomic layer deposition reaction or a chemical vapor deposition reaction.

公开(公告)号：US20170253962A1

公开(公告)日：2017-09-07

申请号：US15447065

申请日：2017-03-01

Applicant: Purdue Research Foundation

Inventor： Sunny Chugh ,  Ruchit Mehta ,  Zhihong Chen

IPC: C23C16/26 ,  C23C16/02 ,  H01L29/16 ,  H01L21/02 ,  H01L21/306 ,  C23C16/505 ,  H01J37/32

CPC classification number: C23C16/26 ,  C01B32/182 ,  C01B32/184 ,  C01B32/186 ,  C23C16/0227 ,  C23C16/505 ,  H01J37/32082 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02527 ,  H01L21/0262 ,  H01L29/1608

Abstract: A graphene deposition process. The process includes the steps of placing a substrate into a deposition chamber and heating the chamber, generating radio frequency plasma at a location proximate to the substrate while flowing a precursor gas containing carbon through the plasma and over the substrate.

公开(公告)号：US09741546B2

公开(公告)日：2017-08-22

申请号：US13629267

申请日：2012-09-27

Applicant: Applied Materials, Inc.

Inventor： James D. Carducci ,  Hamid Tavassoli ,  Ajit Balakrishna ,  Zhigang Chen ,  Andrew Nguyen ,  Douglas A. Buchberger, Jr. ,  Kartik Ramaswamy ,  Shahid Rauf ,  Kenneth S. Collins

IPC: C23C16/00 ,  C23F1/00 ,  H01L21/306 ,  H01J37/32 ,  H05H1/46

CPC classification number: H01J37/3244 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32495 ,  H01J37/32541 ,  H01J37/32568 ,  H01J37/32724 ,  H01J37/32733 ,  H01J37/32743 ,  H01J37/32834 ,  H01J2237/3321 ,  H01J2237/3323 ,  H01J2237/3344 ,  H05H1/46

Abstract: Embodiments of the present invention provide a plasma chamber design that allows extremely symmetrical electrical, thermal, and gas flow conductance through the chamber. By providing such symmetry, plasma formed within the chamber naturally has improved uniformity across the surface of a substrate disposed in a processing region of the chamber. Further, other chamber additions, such as providing the ability to manipulate the gap between upper and lower electrodes as well as between a gas inlet and a substrate being processed, allows better control of plasma processing and uniformity as compared to conventional systems.

公开(公告)号：US20170236689A1

公开(公告)日：2017-08-17

申请号：US15587129

申请日：2017-05-04

Applicant: Applied Materials, Inc.

Inventor： Jonghoon BAEK ,  Soonam PARK ,  Xinglong CHEN ,  Dmitry LUBOMIRSKY

IPC: H01J37/32

CPC classification number: H01J37/32082 ,  C23C16/4401 ,  C23C16/4404 ,  C23C16/503 ,  C23C16/509 ,  C23C16/52 ,  H01J37/32091 ,  H01J37/32146 ,  H01J37/32532 ,  H01J37/3255 ,  H01J37/32568 ,  H01J37/32697 ,  H01J2237/334

Abstract: Embodiments of the present disclosure generally relate to a method for reducing particle generation in a processing chamber. In one embodiment, the method includes generating a plasma between a first electrode and a second electrode of the processing chamber by applying a radio frequency (RF) power to the first electrode during an etch process, wherein the first electrode is disposed above the second electrode, and the second electrode is disposed above and opposing a substrate support having a substrate supporting surface, and applying a constant zero DC bias voltage to the first electrode during the process.

公开(公告)号：US20170229328A1

公开(公告)日：2017-08-10

申请号：US15581545

申请日：2017-04-28

Applicant: Applied Materials, Inc.

Inventor： David Benjaminson ,  Dmitry Lubomirsky ,  Ananda Seelavanth Math ,  Saravanakumar Natarajan ,  Shubham Chourey

IPC: H01L21/67 ,  H01L21/687 ,  H01J37/32 ,  H01L21/324

CPC classification number: H01L21/67103 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32724 ,  H01L21/324 ,  H01L21/68742 ,  H01L21/68785

Abstract: A workpiece holder includes a puck, first and second heating devices in thermal communication with respective inner and outer portions of the puck, and a thermal sink in thermal communication with the puck. The first and second heating devices are independently controllable, and the first and second heating devices are in greater thermal communication with the puck, than thermal communication of the thermal sink with the puck. A method of controlling temperature distribution of a workpiece includes flowing a heat exchange fluid through a thermal sink to establish a reference temperature to a puck, raising temperatures of radially inner and outer portions of the puck to first and second temperatures greater than the reference temperature, by activating respective first and second heating devices disposed in thermal communication with the radially inner and outer portions of the puck, and placing the workpiece on the puck.