公开(公告)号：US20020123285A1

公开(公告)日：2002-09-05

申请号：US09783538

申请日：2001-02-15

Inventor： David E. Dana ,  Vedagiri Velpari ,  Langqiu Xu ,  Charles Kahle ,  Bruce Novich

IPC: B32B005/02 ,  B32B003/00 ,  B32B009/00 ,  D03D015/00 ,  D03D025/00 ,  B32B015/16

CPC classification number: H05K1/0373 ,  C03C25/47 ,  H05K1/036 ,  H05K3/0047 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0245 ,  H05K2201/029 ,  H05K2201/068 ,  H05K2201/0769 ,  H05K2203/127 ,  Y10T442/20 ,  Y10T442/30 ,  Y10T442/3455

Abstract: The present invention provides an electronic support comprising: (A) at least one woven fiber reinforcement material formed from at least one fiber free of basalt glass; and (B) at least one matrix material in contact with at least a portion of the at least one reinforcement material, the at least one matrix material comprising at least one non-fluorinated polymer and at least one inorganic filler, wherein the at least one inorganic filler comprises at least one non-hydratable, lamellar inorganic solid lubricant having a high electrical resistivity and wherein the at least one inorganic filler comprises at least 6 weight percent of a total combined weight of the at least one inorganic filler and the at least one matrix material on a total solids basis.

Abstract translation: 本发明提供一种电子支撑体，包括：（A）由至少一种不含玄武岩纤维的纤维形成的至少一种编织纤维增强材料; 和（B）与所述至少一种增强材料的至少一部分接触的至少一种基质材料，所述至少一种基质材料包含至少一种非氟化聚合物和至少一种无机填料，其中所述至少一种 无机填料包含至少一种具有高电阻率的不可水合的层状无机固体润滑剂，并且其中所述至少一种无机填料占至少一种无机填料和至少一种无机填料的总重量的至少6重量％ 基体材料。

公开(公告)号：US20020085888A1

公开(公告)日：2002-07-04

申请号：US09783540

申请日：2001-02-15

Inventor： Vedagiri Velpari ,  Charles B. Greenberg ,  Bruce E. Novich

IPC: B23B035/00

CPC classification number: H05K3/0047 ,  C03C25/47 ,  H05K1/036 ,  H05K1/0373 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0245 ,  H05K2201/029 ,  H05K2201/068 ,  H05K2201/0769 ,  H05K2203/127 ,  Y10T408/03 ,  Y10T408/44 ,  Y10T408/455

Abstract: The present invention provides a method of forming an aperture in an electronic support, comprising: (A) positioning an electronic support in registry with an aperture forming device; and (B) forming an aperture at least partially through the electronic support with the aperture forming device while dispensing a fluid stream comprising at least one solid lubricant, proximate the aperture forming device during at least a position of the forming, such that the at least one solid lubricant contacts at least a portion of an interface between the aperture forming device and the electronic support.

Abstract translation: 本发明提供了一种在电子支架中形成孔的方法，包括：（A）将电子支架定位成与孔形成装置成对准; 和（B）至少部分地通过所述孔形成装置通过所述电子支撑件形成孔，同时在所述成形的至少一个位置期间分配包括至少一种固体润滑剂的流体流，所述至少一种固体润滑剂在所述孔形成装置附近，使得至少 一个固体润滑剂接触孔形成装置和电子支架之间的界面的至少一部分。

公开(公告)号：US6411194B2

公开(公告)日：2002-06-25

申请号：US79459601

申请日：2001-02-27

Applicant: VICTOR COMPANY OF JAPAN

Inventor： SHINDOH MOTOSHI ,  SEGAWA KEIJI ,  OTSUKI MITSURU

IPC: H01C17/12 ,  H05K1/02 ,  H05K1/16 ,  H05K3/38 ,  H05K3/46 ,  H01C1/012

CPC classification number: H05K1/167 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board. The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board.

Abstract translation: 本发明提供一种能够形成在印刷电路板中具有高精度的厚度和形状的薄膜电阻元件的制造方法。 形成在印刷电路板上的薄膜电阻元件的制造方法具有以下步骤：通过用于制造半导体的干法在印刷电路板上形成具有预定厚度的薄膜电阻层，形成 在所述薄电阻层上的导电层，并且选择性地蚀刻所述导电层，以便至少形成一对导电焊盘，导致所述薄膜电阻元件在所述一对电学上具有预定的电阻率值 导电垫。 因此，可以在印刷电路板上形成具有高精度的厚度和形状的薄膜电阻元件。

公开(公告)号：US06370012B1

公开(公告)日：2002-04-09

申请号：US09652596

申请日：2000-08-30

Applicant: Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

Inventor： Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

IPC: H01G4228

CPC classification number: H05K1/053 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/162 ,  H05K3/403 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0919 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/417 ,  H01L2924/00

Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Abstract translation: 能够形成较大的电路板或类似结构的内部部分以提供电容的并联电容器结构。 或者，电容器可以用作互连器以互连两个不同的电子部件（例如，芯片载体，电路板，甚至半导体芯片），同时仍然为一个或多个所述部件提供期望的电容水平。 电容器包括至少一个内部导电层，在内部导体的相对侧上添加两个附加的导体层，以及无机介电材料（优选地，在第二导体层的外表面上的氧化物层或适用于诸如钛酸钡的适当介电材料 第二导体层）。 此外，电容器包括无机介电材料顶部的外部导体层，从而在内部和附加的导电层和外部导体之间形成并联的电容器。

公开(公告)号：US20020014841A1

公开(公告)日：2002-02-07

申请号：US09903495

申请日：2001-07-13

Inventor： Masashi Nishiki ,  Ryohei Satoh ,  Yuzo Taniguchi ,  Shigeaki Suzuki ,  Michifumi Kawai ,  Masahito Ijuin ,  Akira Yabushita ,  Makoto Fukushima ,  Tomohiko Murase

IPC: H01J017/49

CPC classification number: H05K3/062 ,  H01J9/02 ,  H01J11/12 ,  H01J11/22 ,  H01J11/24 ,  H01J2211/225 ,  H05K3/04 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0326 ,  H05K2203/025 ,  H05K2203/107

Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.

公开(公告)号：US06339197B1

公开(公告)日：2002-01-15

申请号：US09579270

申请日：2000-05-26

Applicant: Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

Inventor： Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

IPC: H01R1204

CPC classification number: H05K3/426 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 &mgr;m thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract translation: 允许形成精细布线图案的多层印刷布线板，从而增加布线图案的密度。 使用具有与铜膜接近的热膨胀系数的感光性玻璃作为芯基板，通过光刻在感光性玻璃中形成通孔，形成溅射氧化硅层和溅射氮化硅层，以防止泄漏 形成来自感光玻璃的碱金属离子，溅射铬层，溅射铬 - 铜层和溅射铜层，以提高铜膜和溅射氧化硅层之间的粘合强度，并使铜膜为1〜20 形成了厚厚的妈妈。 当树脂填充到通孔的内部时，通过蚀刻对布线层进行图案化，形成绝缘层，并且表面被表面处理层和覆盖层覆盖。

公开(公告)号：US06323096B1

公开(公告)日：2001-11-27

申请号：US09162800

申请日：1998-09-29

Applicant: Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

Inventor： Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

IPC: H01L2170

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/19 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/162 ,  H05K1/167 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Abstract translation: 制造柔性互连膜的方法包括在电介质膜的一个或两个表面上施加电阻层; 在所述电阻层上施加金属化层，所述电阻层包括促进所述电介质膜和所述金属化层的粘附的材料; 在所述金属化层上施加电容器电介质层; 以及在电容器电介质层上施加电容器电极层。 将电容器电极层图案化以形成第一电容器电极; 对电容器电介质层进行图案化; 图案化金属化层以形成电阻器; 并且金属化层和电阻层被图案化以形成电感器和第二电容器电极。 在一个实施例中，电介质膜包括聚酰亚胺，电阻层包括氮化钽，电容器介电层包括无定形氢化碳或氧化钽。 如果将电阻和金属化层施加在电介质膜的两个表面上，则可以在电介质膜的两个表面上制造无源元件。 电介质膜可以具有通孔，其中电阻器和金属化层延伸穿过通孔。 电路芯片可以通过在附加电介质层中通过通孔图案化的金属化而附接并耦合到无源部件。

公开(公告)号：US5629241A

公开(公告)日：1997-05-13

申请号：US499800

申请日：1995-07-07

Applicant: Mehran Matloubian ,  Perry A. Macdonald ,  David B. Rensch ,  Lawrence E. Larson

Inventor： Mehran Matloubian ,  Perry A. Macdonald ,  David B. Rensch ,  Lawrence E. Larson

IPC: H01L21/60 ,  H01L23/66 ,  H01P3/08 ,  H01Q23/00 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L25/162 ,  H01L23/66 ,  H01L24/81 ,  H01Q23/00 ,  H05K3/3452 ,  H01L2223/6677 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0237 ,  H05K2201/0175 ,  H05K2203/0315

Abstract: A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates. In a self-contained antenna application in which two of the circuit substrates are laminated together, with an antenna on one side and circuitry on the other side, a metallic ground plane between the substrates also serves a stiffening function.

Abstract translation: 微波/毫米波电路结构通过倒装芯片安装到低成本非陶瓷和非半导体电介质基底（优选为Duroid）上的互连网络来支持分立电路元件。 通过氧化互连网络来提供电路元件与高工作频率所需的基板网络上的接触焊盘的必要精确对准，但是提供来自不可氧化材料的接触焊盘以建立用于焊盘的优先焊料凸块润湿 。 或者，倒装芯片上的接触凸块可以通过互连网络上的钝化层中的相应开口精确定位。 对于对于成功倒装芯片安装来说太软的薄电路基板，加固基板被层压到电路基板上。 在其中两个电路基板层叠在一起的独立天线应用中，一侧的天线和另一侧的电路，在基板之间的金属接地平面也起增强作用。

公开(公告)号：US5509200A

公开(公告)日：1996-04-23

申请号：US342506

申请日：1994-11-21

Applicant: Jerome A. Frankeny ,  Richard F. Frankeny ,  Ronald L. Imken ,  Keith A. Vanderlee

Inventor： Jerome A. Frankeny ,  Richard F. Frankeny ,  Ronald L. Imken ,  Keith A. Vanderlee

IPC: H01L23/538 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/44 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/462 ,  H01L23/5385 ,  H05K1/112 ,  H05K1/162 ,  H05K3/445 ,  H05K3/4641 ,  H01L2224/16225 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0307 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/4623 ,  Y10S428/901 ,  Y10T29/49165

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability.

Abstract translation: 用于制造精细间距图案多层印刷电路板的方法和装置，其包括提供功率分配，信号分配和电容去耦的层叠堆叠板层。 在一个方面，本发明涉及通过金属芯开始制造板层，图案化芯，选择性地将芯包围在电介质中，选择性地沉积金属以形成通孔，插塞和信号线，以及用连接冶金形成树突 在通孔和插头上，以从板层的平面上方或下方提供可堆叠连接。 在另一方面，本发明涉及使用溶胶 - 凝胶法在金属片上形成薄的高介电常数结晶膜，随后在高介电常数膜上沉积金属层。 该膜用作电容器层的电介质，其后连续地被图案化，被电介质覆盖，并且已经选择性地沉积用于互连电容器和形成通孔的金属层。 然后通孔的端部经历树枝状生长并连接冶金以提供可堆叠的互连能力。

公开(公告)号：US5347091A

公开(公告)日：1994-09-13

申请号：US933424

申请日：1992-08-21

Applicant: Donald R. Schroeder

Inventor： Donald R. Schroeder

IPC: H01L23/367 ,  H01L23/538 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/18 ,  H05K3/40 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0206 ,  H01L23/3672 ,  H01L23/5385 ,  H05K3/4605 ,  H05K3/4629 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/181 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/10674 ,  H05K2203/061 ,  H05K2203/1572 ,  H05K3/4061 ,  H05K3/4614

Abstract: A multilayer circuit card is disclosed that interconnects multichip modules to each other electrically, and simultaneously acts to dissipate otherwise destructive thermal energy. The circuit card is comprised by an aluminum nitride core and two opposed low temperature co-fired ceramic laminates, all three laminated to each other.

Abstract translation: 公开了一种多层电路卡，其将多芯片模块彼此电连接起来，并且同时作用以消散否则具有破坏性的热能。 电路卡由氮化铝芯和两个相对的低温共烧陶瓷层压体组成，全部三个层叠。