公开(公告)号：US20050140434A1

公开(公告)日：2005-06-30

申请号：US11010327

申请日：2004-12-14

Applicant: Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

Inventor： Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

IPC: H01L23/12 ,  H03F3/195 ,  H03F3/60 ,  H03G3/30 ,  H05K1/02 ,  H05K1/16 ,  H05K3/24 ,  H05K3/46 ,  H03F1/00

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.

Abstract translation: 本发明的电感器元件电路板包括多个导电层，以及在一个或多个导电层中具有电感器功能（电感器导体段）的导体，其中电感器导体段的至少一部分变厚 而不是设置在电路板内的其它导线。 电感器导体段的至少一部分延伸穿过设置在导电层之间的绝缘层，或者嵌入在绝缘层中，其中电感器导体段的一部分具有绝缘层的厚度的一半或更多的厚度 。 本发明的功率放大器模块包括多层电路板，在多层电路板中制造的半导体放大器和耦合到半导体放大器的输出的阻抗匹配电路。 阻抗匹配电路具有由电感器导体段形成的部分。

公开(公告)号：US06872590B2

公开(公告)日：2005-03-29

申请号：US10626437

申请日：2003-07-24

Applicant: Jong-Jin Lee ,  Tae-Gui Kim

Inventor： Jong-Jin Lee ,  Tae-Gui Kim

IPC: H01L23/12 ,  H01L21/48 ,  H05K3/02 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H01L21/44

CPC classification number: H05K3/243 ,  H01L21/4846 ,  H01L21/4857 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/064 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1394 ,  H05K2203/1476 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed is a package substrate for electrolytic leadless plating, characterized in that a wire bonding pad onto which a semiconductor chip is mounted is subjected to electrolytic leadless Au plating, and a solder ball pad is subjected to OSP metal finishing or electroless Au plating without use of plating lead lines, upon preparation thereof. A method of manufacturing the package substrate is also disclosed. The method includes Cu plating a whole surface of a base substrate having through-holes, developing a first dry film laminated onto the through-holes, removing a copper foil not covered with the first dry film, stripping the first dry film, exposing and developing a second dry film on the substrate so that only an upper portion to be subjected to electrolytic Au plating is exposed, grounding an electrolytic Au plating terminal to a solder ball pad, Ni—Au plating the wire bonding pad, removing the second dry film by a stripping solution, exposing and developing a third dry film, removing the exposed copper foil by an etching solution, removing the third dry film by a stripping solution, performing a series of processes of coating, exposing, developing and drying a solder resist, and subjecting the solder ball pad to OSP metal finishing.

Abstract translation: 公开了一种用于电解无铅电镀的封装衬底，其特征在于，对其上安装有半导体芯片的引线焊盘进行电解无铅镀Au，并且焊球垫经受OSP金属整理或无电镀Au，而不使用 电镀引线在制备时。 还公开了一种制造封装衬底的方法。 该方法包括对具有通孔的基底基板的整个表面进行镀铜，形成层压在通孔上的第一干膜，除去未被第一干膜覆盖的铜箔，剥离第一干膜，曝光和显影 在基板上的第二干膜，使得只有待进行电解Au电镀的上部暴露，将电解Au电镀端子接地到焊球垫，Ni-Au电镀引线接合焊盘，通过以下步骤除去第二干膜 剥离溶液，曝光和显影第三干膜，通过蚀刻溶液除去暴露的铜箔，通过剥离溶液除去第三干膜，进行一系列涂布，曝光，显影和干燥阻焊剂的工艺，以及 对焊锡球进行OSP金属加工。

公开(公告)号：US20040266070A1

公开(公告)日：2004-12-30

申请号：US10612282

申请日：2003-06-30

Inventor： Charan K. Gurumurthy ,  Hamid Azimi ,  Arthur K. Lin

IPC: H01L021/44

CPC classification number: H05K3/243 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2203/1572 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.

Abstract translation: 一种形成可适于附接到一个或多个电子部件的集成电路基板的方法。 该方法包括将抗蚀剂涂覆在基板的背面，该基板在基板的正面和背面包括图案化的导电层。 该方法还包括从衬底的前侧去除图案化的导电层的一部分，以在衬底的正面上形成焊盘和互连，并将另一个抗蚀剂施加到衬底的正面。 该方法还包括在每个抗蚀剂中形成图案，其暴露衬底的正面和背面上的焊盘并将电解镍施加到衬底上的焊盘。

公开(公告)号：US06831357B2

公开(公告)日：2004-12-14

申请号：US10397608

申请日：2003-03-26

Applicant: Yuji Nishitani ,  Tsuyoshi Ogawa ,  Hiroshi Asami ,  Akihiko Okubora

Inventor： Yuji Nishitani ,  Tsuyoshi Ogawa ,  Hiroshi Asami ,  Akihiko Okubora

IPC: H01L2348

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/19041 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/467 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2203/061

Abstract: A circuit substrate device composed of a circuit unit 2 and a multi-layer wiring substrate 3 in which a pattern conductor of the circuit unit 2 may be prevented from being warped or inundated. The circuit substrate device includes a circuit unit 2 having a pattern conductor formed by a thin film technique, and an insulating layer, and a multi-layer wiring substrate 3 having a connecting terminal portion 14 exposed from its major surface. The circuit unit is formed on a dummy substrate. The circuit unit is connected to the multi-layer wiring substrate 3 so that the pattern conductor is connected to the connecting terminal portion 14. The dummy substrate is then removed to give a structure comprised of the circuit unit 2 formed on the multi-layer wiring substrate 3. The pattern conductor of the circuit unit 2 is freed of warping or inundations along the direction of thickness of the circuit unit 2.

公开(公告)号：US20040229024A1

公开(公告)日：2004-11-18

申请号：US10814804

申请日：2004-04-01

Inventor： Toshikazu Harada ,  Koji Kondo

IPC: B32B003/00

CPC classification number: H05K1/0242 ,  H05K1/024 ,  H05K3/382 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2203/065 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T428/24917

Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.

Abstract translation: 多层印刷电路板包括绝缘基板; 设置在所述绝缘基板的表面上的表面导电图案; 以及嵌入绝缘基板中的内导电图案。 表面导电图案在绝缘基板侧具有表面粗糙度，表面导电图案的表面粗糙度大于内部导电图案的表面粗糙度。

公开(公告)号：US06735052B2

公开(公告)日：2004-05-11

申请号：US10259005

申请日：2002-09-27

Applicant: Christopher G. Dunn ,  Nathan P. Kreutter

Inventor： Christopher G. Dunn ,  Nathan P. Kreutter

IPC: G11B548

CPC classification number: H05K1/0281 ,  G11B5/4826 ,  G11B5/484 ,  H05K1/056 ,  H05K3/108 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/2009

Abstract: A disk drive suspension assembly including an elongated polymeric base member having a plurality of traces formed directly on a first surface thereof and a reference voltage layer formed on a second surface thereof. A support member is formed directly on at least a portion of the reference voltage layer. The plurality of traces overlay at least a portion of the reference voltage layer. The reference voltage layer is formed from a first electrically conductive material and the support member is formed from a second electrically conductive material. The first electrically conductive material providing substantially greater electrical conductivity and substantially less tensile strength than the second electrically conductive material. The support member includes a head gimbal portion having a first thickness and a load beam portion having a second thickness. The second thickness is substantially greater than the first thickness.

Abstract translation: 一种磁盘驱动器悬架组件，其包括细长的聚合物基底构件，其具有直接形成在其第一表面上的多个迹线和在其第二表面上形成的参考电压层。 支撑构件直接形成在参考电压层的至少一部分上。 多个迹线覆盖参考电压层的至少一部分。 参考电压层由第一导电材料形成，并且支撑构件由第二导电材料形成。 第一导电材料提供比第二导电材料显着更大的导电性和显着更小的拉伸强度。 支撑构件包括具有第一厚度的头部万向节部分和具有第二厚度的负载梁部分。 第二厚度基本上大于第一厚度。

公开(公告)号：US06677521B2

公开(公告)日：2004-01-13

申请号：US10418168

申请日：2003-04-18

Applicant: Tatsuya Sumida ,  Yuuji Saka ,  Noriko Kobayashi ,  Hisaki Mayumi

Inventor： Tatsuya Sumida ,  Yuuji Saka ,  Noriko Kobayashi ,  Hisaki Mayumi

IPC: H02G308

CPC classification number: B60R16/0238 ,  B60R16/0239 ,  H05K1/0289 ,  H05K7/026 ,  H05K2201/0352 ,  H05K2201/10272 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: An electrical junction box for a vehicle has a casing, and an electrical circuit comprising a fuse connection circuit, a relay connection circuit and a connector connection circuit. The casing has, at opposite sides, connector sockets for electrical connectors. In the casing is a connector module comprising a plurality of insulation substrates stacked one on another and parallel elongated bus bars on a first surface of each substrate and parallel flexible conductors on a second surface of the substrate, which extend orthogonally to said bus bars. Each said insulation substrate has apertures through it at which the bus bars and flexible conductors are connected to each other to provide desired circuit connections. The bus bars extend from the insulation substrates and provide tabs projecting into the connector sockets. A thin junction box is obtained.

Abstract translation: 一种用于车辆的电接线盒具有壳体和包括熔丝连接电路，继电器连接电路和连接器连接电路的电路。 壳体在相对侧具有用于电连接器的连接器插座。 在壳体中是连接器模块，该连接器模块包括多个彼此层叠的绝缘基板和在每个基板的第一表面上的平行的细长汇流条，并且在基板的第二表面上的平行的柔性导体，其垂直于所述汇流条延伸。 每个所述绝缘衬底具有穿过其的孔，母线和柔性导体彼此连接以提供期望的电路连接。 汇流条从绝缘基板延伸，并提供突出到连接器插座中的突出部。 得到一个细接线盒。

公开(公告)号：US20030214027A1

公开(公告)日：2003-11-20

申请号：US10397608

申请日：2003-03-26

Inventor： Yuji Nishitani ,  Tsuyoshi Ogawa ,  Hiroshi Asami ,  Akihiko Okubora

IPC: H01L023/053

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/19041 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/467 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2203/061

Abstract: A circuit substrate device composed of a circuit unit 2 and a multi-layer wiring substrate 3 in which a pattern conductor of the circuit unit 2 may be prevented from being warped or inundated. The circuit substrate device includes a circuit unit 2 having a pattern conductor formed by a thin film technique, and an insulating layer, and a multi-layer wiring substrate 3 having a connecting terminal portion 14 exposed from its major surface. The circuit unit is formed on a dummy substrate. The circuit unit is connected to the multi-layer wiring substrate 3 so that the pattern conductor is connected to the connecting terminal portion 14. The dummy substrate is then removed to give a structure comprised of the circuit unit 2 formed on the multi-layer wiring substrate 3. The pattern conductor of the circuit unit 2 is freed of warping or inundations along the direction of thickness of the circuit unit 2.

Abstract translation: 由电路单元2和多层布线基板3构成的电路基板装置，其中可以防止电路单元2的图形导体翘曲或被淹没。 电路基板装置包括具有通过薄膜技术形成的图案导体的电路单元2和绝缘层，以及具有从其主表面露出的连接端子部分14的多层布线基板3。 电路单元形成在虚设基板上。 电路单元连接到多层布线基板3，使得图案导体连接到连接端子部分14.然后去除虚设基板以给出由形成在多层布线上的电路单元2构成的结构 基板3.电路单元2的图案导体沿着电路单元2的厚度方向不会发生翘曲或淹没。

公开(公告)号：US20020185311A1

公开(公告)日：2002-12-12

申请号：US09876522

申请日：2001-06-07

Inventor： Charles Cohn

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K3/243 ,  H05K3/062 ,  H05K3/108 ,  H05K3/242 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2203/0571 ,  H05K2203/1572 ,  H05K2203/1581

Abstract: The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.

Abstract translation: 本发明提供了一种在由芯的两侧具有电介质层的刚性双面或多层印刷线路板芯制造的集成电路（IC）基板上电镀电接触的方法。 该方法可以包括在基板的第一和第二相对侧上形成电连接的镀层，并且使用镀层在每个镀层上电镀接触层。 该方法还包括从第一和第二相对侧去除一部分镀层，同时将镀层留在接触层下方。

公开(公告)号：US20020137347A1

公开(公告)日：2002-09-26

申请号：US09815226

申请日：2001-03-22

Inventor： Bharat Z. Patel ,  Jay D. Baker ,  Lakhi N. Goenka ,  Michael Allen Howey ,  Mohan R. Paruchuri ,  Richard Keith McMillan

IPC: H01L021/311

CPC classification number: H05K3/44 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1184

Abstract: A method 10 for making a multi-layer circuit board 70 having at least one electrically conductive interconnection portion or nullvianull 72 which extends within the board 70 and at least one air-bridge 74. The method 10 includes the steps of forming protuberances 13 upon a core member 12, attaching pre-circuit assemblies 32, 34 to the core member 12, thereby forming the circuit board 70 while concomitantly and selectively extending at least one of the protuberances 13 within the formed circuit board 70.

Abstract translation: 制造多层电路板70的方法10具有至少一个在板70内和至少一个空气桥74上延伸的导电互连部分或“通孔”72。方法10包括以下步骤：形成突起13 在芯构件12上，将预电路组件32,34附接到芯构件12，从而形成电路板70，同时并且选择性地延伸形成的电路板70内的至少一个突起13。