公开(公告)号：US20080121420A1

公开(公告)日：2008-05-29

申请号：US11557711

申请日：2006-11-08

Applicant: Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

Inventor： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

IPC: H05K1/00

CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476

Abstract: Closed vias are formed in a multilayer printed circuit board by laminating a dielectric layer to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

Abstract translation: 通过在每侧具有金属层的中心芯的一侧层叠电介质层，在多层印刷电路板中形成封闭的通孔。 第二电介质层被层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。 来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。

公开(公告)号：US20080119041A1

公开(公告)日：2008-05-22

申请号：US11557690

申请日：2006-11-08

Applicant: Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

Inventor： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

IPC: H05K3/30 ,  H01L21/4763

CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

Abstract translation: 一种在多层印刷电路板中形成封闭通孔的方法。 电介质层被层叠在每侧具有金属层的中心芯的一侧。 第二电介质层被层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。 来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。

公开(公告)号：US07362113B2

公开(公告)日：2008-04-22

申请号：US10005402

申请日：2001-12-05

Applicant: Alan G. Wood ,  Tim J. Corbett

Inventor： Alan G. Wood ,  Tim J. Corbett

IPC: G01R31/02

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract translation: 用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

公开(公告)号：US07356907B2

公开(公告)日：2008-04-15

申请号：US10997005

申请日：2004-11-24

Applicant: Kenji Kobae ,  Takashi Kubota

Inventor： Kenji Kobae ,  Takashi Kubota

IPC: G11B5/127 ,  H04R31/00

CPC classification number: G11B5/486 ,  G11B5/4833 ,  G11B5/4846 ,  H05K1/056 ,  H05K3/363 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2203/0285 ,  Y10T29/49025 ,  Y10T29/49027 ,  Y10T29/4903

Abstract: A method of manufacturing a cartridge assembly of a hard disk drive, including a step of forming a part of a wiring circuit into flying leads and a step of forming a coating layer on the respective opposite surfaces of the bonding surfaces of the flying leads, which will be connected to bonding terminals of a flexible printed circuit board. The method also includes a step of placing an ultrasonic tool in contact with the opposite surfaces of the flying leads via the coating layers, and applying ultrasonic vibration from the ultrasonic tool in a state where the flying leads are pressed onto the bonding terminals to ultrasonically bond the flying leads and the bonding terminals together. Additionally, the method includes a step of heating and melting the coating layers to smooth surfaces of the coating layers that have been roughened by contact with the ultrasonic tool during ultrasonic bonding.

Abstract translation: 一种制造硬盘驱动器的盒组件的方法，包括将布线电路的一部分形成为飞行引线的步骤以及在飞线的接合表面的相应相对表面上形成涂层的步骤，其中 将连接到柔性印刷电路板的接合端子。 该方法还包括将超声波工具经由涂层与飞线的相对表面接触的步骤，以及在将飞行引线按压到接合端子上以超声波接合的状态下从超声波工具施加超声波振动 飞线和接合端子在一起。 此外，该方法包括以下步骤：在超声波接合期间，通过与超声波工具的接触使加热和熔化涂层以平滑已经被粗糙化的涂层的表面。

公开(公告)号：US20080083554A1

公开(公告)日：2008-04-10

申请号：US11538637

申请日：2006-10-04

Applicant: Robert G. Biskeborn ,  George G. Zamora

Inventor： Robert G. Biskeborn ,  George G. Zamora

IPC: H01B7/08

CPC classification number: H05K3/361 ,  H01L2224/48091 ,  H05K3/328 ,  H05K3/4092 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/10659 ,  H05K2203/049 ,  H01L2924/00014

Abstract: A flexible circuit for bonding to another circuit includes a film having a first conductor layer fabricated upon a topside of the film and a second conductor layer fabricated on an underside of the film, the first conductor layer being insulated by a first insulator layer fabricated thereover, the second conductor layer being insulated by a second insulator layer fabricated thereover; wherein the first conductor layer terminates in at least one bonding pad for the bonding to the another circuit and the second conductor layer terminates in at least one finger lead for the bonding to another circuit. A method for fabricating the flex circuit is provided.

Abstract translation: 用于接合到另一电路的柔性电路包括具有在膜顶部制造的第一导体层的膜和在膜的下侧制造的第二导体层，第一导体层由其上制造的第一绝缘体层绝缘， 所述第二导体层由制造在其上的第二绝缘体层绝缘; 其中所述第一导体层终止于至少一个用于与所述另一电路接合的接合焊盘，并且所述第二导体层终止于用于与另一电路接合的至少一根指状引线。 提供了制造柔性电路的方法。

公开(公告)号：US07348215B2

公开(公告)日：2008-03-25

申请号：US10150901

申请日：2002-05-17

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L21/44

CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/16237 ,  H01L2224/8014 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor device assembly. The flip chip-type semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having a plurality of recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the plurality of recesses so that the die face is adjacent the facing surface of the interposer substrate. One or more openings may be provided in an opposing surface of the interposer substrate which extend to the plurality of recesses and the conductive bumps disposed therein. Dielectric filler material may then be introduced through the one or more openings to the recesses and, optionally, between the semiconductor die and interposer substrate.

Abstract translation: 一种用于将一个或多个倒装芯片配置的半导体管芯与内插器衬底组装和封装以形成倒装芯片型半导体器件组件的方法。 倒装芯片型半导体器件组件包括导电凸起的半导体管芯和在其中形成有多个凹槽的插入器衬底。 将半导体管芯安装到插入器基板上，其中导电凸块设置在多个凹部中，使得模具表面邻近插入器基板的相对表面。 可以在插入器基板的相对表面中设置一个或多个开口，该表面延伸到多个凹部和设置在其中的导电凸块。 然后可以将介质填充材料通过一个或多个开口引入到凹部中，并且可选地在半导体管芯和插入器衬底之间引入。

公开(公告)号：US20080055873A1

公开(公告)日：2008-03-06

申请号：US11896036

申请日：2007-08-29

Applicant: Xiaoyu Mi ,  Tsuyoshi Matsumoto ,  Satoshi Ueda

Inventor： Xiaoyu Mi ,  Tsuyoshi Matsumoto ,  Satoshi Ueda

IPC: H05K1/16 ,  H05K3/00 ,  H05K7/02

CPC classification number: H05K1/165 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19015 ,  H05K1/162 ,  H05K3/0052 ,  H05K3/4685 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/308 ,  Y10T29/49124 ,  H01L2224/0401

Abstract: An electronic part module includes a wiring substrate, a passive device group of passive devices formed on the wiring substrate, and device chips mounted on the wiring substrate. Such an electronic part module is made in the following manner. First, a wiring substrate wafer is made, to include a plurality of electronic part module formation areas. Then, a plurality of passive devices are formed in each of the electronic part module formation areas on the wiring substrate wafer. Then, the device chips are formed on each of the electronic part module formation areas on the wiring substrate wafer. Finally, the wiring substrate wafer is divided.

Abstract translation: 电子部件模块包括布线基板，形成在布线基板上的无源器件的无源器件组以及安装在布线基板上的器件芯片。 这样的电子部件模块以如下方式制成。 首先，制造布线基板晶片，以包括多个电子部件模块形成区域。 然后，在布线基板晶片上的每个电子部件模块形成区域中形成多个无源器件。 然后，在布线基板晶片上的每个电子部件模块形成区域上形成器件芯片。 最后，分配布线基板晶片。

公开(公告)号：US07318729B2

公开(公告)日：2008-01-15

申请号：US10515062

申请日：2003-10-24

Applicant: Katsumi Sato ,  Kazuo Inoue

Inventor： Katsumi Sato ,  Kazuo Inoue

IPC: H01R12/00 ,  H05K1/00

CPC classification number: G01R1/07314 ,  G01R1/06711 ,  G01R1/06733 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R11/01 ,  H01R12/523 ,  H05K1/116 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2203/0733 ,  H01L2924/00

Abstract: Disclosed herein are a sheet-like connector that electrode structures each having a front-surface electrode part small in diameter can be formed, a stable electrically connected state can be surely achieved even to a circuit device, on which electrodes have been formed at a small pitch, and the electrode structures are prevented from falling off from an insulating sheet to achieve high durability, and a production process and applications thereof.The sheet-like connector of the invention has an insulating sheet and a plurality of electrode structures arranged in the insulating sheet and extending through in a thickness-wise direction of the insulating sheet. Each of the electrode structures is composed of a front-surface electrode part exposed to a front surfaces of the insulating sheet and projected from the front surface of the insulating sheet, a back-surface electrode part exposed to a back surface of the insulating sheet, a short circuit part continuously extending from the base end of the front-surface electrode part through the insulating sheet in the thickness-wise direction thereof and linked to the back-surface electrode part, and a holding part continuously extending from a base end portion of the front-surface electrode part outward along the front surface of the insulating sheet.

Abstract translation: 这里公开了一种片形连接器，其可以形成具有直径小的前表面电极部分的电极结构，甚至可以可靠地获得稳定的电连接状态，其中电路已经形成在小电极 节距，并且防止电极结构从绝缘片脱落以实现高耐久性，以及其制造方法和应用。 本发明的片状连接器具有布置在绝缘片中的绝缘片和多个电极结构，并沿绝缘片的厚度方向延伸。 每个电极结构由暴露于绝缘片的前表面并从绝缘片的前表面突出的前表面电极部分，暴露于绝缘片的背面的背面电极部分组成， 从前表面电极部分的基端沿其厚度方向通过绝缘片连续地延伸并连接到背面电极部分的短路部分，以及从背面电极部分的基端部分连续延伸的保持部分， 前表面电极部分沿着绝缘片的前表面向外。

公开(公告)号：US20070263370A1

公开(公告)日：2007-11-15

申请号：US11555881

申请日：2006-11-02

Applicant: AYAO NIKI

Inventor： AYAO NIKI

IPC: H05K1/03

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract translation: 多层印刷线路板包括一个或多个具有通孔的树脂层和具有通孔的芯层。 在一个或多个树脂层中形成的通孔在与芯层中形成的通路孔打开的方向相反的方向上开口。 一种制造多层印刷线路板的方法包括制备单面或双面覆铜层压板的步骤; 通过加工覆铜层压板来形成焊盘的步骤; 在覆铜层压板的上表面上形成树脂层的步骤，在树脂层中形成通孔的开口，然后形成通孔; 以及在覆铜层压板的下表面中形成用于通孔的开口，然后形成通孔的步骤。

公开(公告)号：US07288953B2

公开(公告)日：2007-10-30

申请号：US10799258

申请日：2004-03-12

Applicant: Alan G. Wood ,  Tim J. Corbett

Inventor： Alan G. Wood ,  Tim J. Corbett

IPC: G01R31/28 ,  G01R31/02

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.