公开(公告)号：US20090284909A1

公开(公告)日：2009-11-19

申请号：US12176416

申请日：2008-07-21

Applicant: Chun-Hsin Liu ,  Po-Yuan Liu

Inventor： Chun-Hsin Liu ,  Po-Yuan Liu

IPC: H05K7/06 ,  H05K1/11

CPC classification number: H05K1/025 ,  G02F1/1345 ,  G02F1/13452 ,  G02F2001/13456 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/0784 ,  H05K2201/09263 ,  H05K2201/10674

Abstract: A flat panel display and a chip bonding pad thereof are provided. The flat panel display includes a display panel, an FPC board, first and second source driving chips, and a control circuit board. First and second wires in a peripheral circuit region of the display panel extend from the underneath of the FPC board to two opposite sides of the display panel and electrically connect the FPC board. The first source driving chips electrically connect the FPC board through parts of the first wires. The second source driving chips electrically connect the FPC board through the second wires. The chip bonding pad is under one of the first and second source driving chips. The chip bonding pad includes a first dielectric layer having first through holes and a second dielectric layer having second and third through holes arranged alternately. The second through holes correspond to the first through holes.

Abstract translation: 提供了一种平板显示器及其芯片接合垫。 平板显示器包括显示面板，FPC基板，第一和第二源驱动芯片以及控制电路板。 显示面板的外围电路区域中的第一和第二导线从FPC板的下面延伸到显示面板的两个相对的两侧并将FPC基板电连接。 第一源驱动芯片通过部分第一导线将FPC板电连接。 第二源驱动芯片通过第二线电连接FPC板。 芯片接合焊盘位于第一和第二源极驱动芯片之一之下。 芯片接合焊盘包括具有第一通孔的第一介电层和具有交替布置的第二和第三通孔的第二介电层。 第二通孔对应于第一通孔。

公开(公告)号：US20090283891A1

公开(公告)日：2009-11-19

申请号：US12295782

申请日：2007-04-03

Applicant: Ronald Dekker ,  Theodorus Martinus Michielsen ,  Theodoros Zoumpoulidis

Inventor： Ronald Dekker ,  Theodorus Martinus Michielsen ,  Theodoros Zoumpoulidis

IPC: H01L23/538 ,  H01L21/60

CPC classification number: H05K1/0283 ,  H01L23/5387 ,  H01L24/01 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/007 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2201/09781 ,  H05K2203/016 ,  H05K2203/0271 ,  H01L2924/00

Abstract: The present invention relates to an integrated-circuit device comprising a multitude of separate rigid substrate islands (202 to 208) with circuit elements, a respective substrate island being connected to respective neighbor substrate islands by respective elastically deformable connections 210 to 222), which contain at least one respective signaling layer that is made of an electrically conductive material. At least one elastically deformable connection between substrate islands has a signaling layer, which is not electrically connected and thus forms a dummy signaling layer (210a to 210c), and the elastically deformable connections, which connect a respective substrate island to respective neighbor substrate islands along a first direction, have an elastic deformability in the first direction governed by respective moduli of elasticity, the ratio of which is between 0.5 and 2.0. This reduces the inhomogeneity of strain in the network of substrate islands that is formed by the integrated-circuit device. The functional reliability of the integrated-circuit device of the invention is increased over prior-art devices without restricting the freedom of circuit design.

Abstract translation: 本发明涉及一种集成电路器件，其包括具有电路元件的多个单独的刚性衬底岛（202至208），相应的衬底岛通过相应的可弹性变形的连接210至222连接到相应的相邻衬底岛），其包含 由导电材料制成的至少一个相应的信号层。 衬底岛之间的至少一个可弹性变形的连接具有信号层，其不是电连接的并且因此形成虚拟信令层（210a至210c）以及可弹性变形的连接，其将相应的衬底岛连接到相应的相邻衬底岛 第一方向在第一方向上具有由相应的弹性模量控制的弹性变形能力，其比例在0.5和2.0之间。 这降低了由集成电路器件形成的衬底岛的网络中的应变的不均匀性。 本发明的集成电路器件的功能可靠性比现有技术的器件增加，而不限制电路设计的自由度。

公开(公告)号：US20090283314A1

公开(公告)日：2009-11-19

申请号：US12453473

申请日：2009-05-12

Applicant: Tetsuya Ohsawa ,  Yasunari Ooyabu ,  Jun Ishii

Inventor： Tetsuya Ohsawa ,  Yasunari Ooyabu ,  Jun Ishii

IPC: H05K1/11 ,  H05K3/02

CPC classification number: H05K3/242 ,  G11B5/484 ,  H05K1/056 ,  H05K1/117 ,  H05K3/06 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2203/175

Abstract: A method for producing a wired circuit board includes the steps of integrally forming a conductive pattern, a plating lead electrically connected with the conductive pattern, and a regulation portion provided in the plating lead to regulate penetration of an etchant into the conductive pattern; and etching the plating lead with the etchant while the regulation portion regulates the penetration of the etchant into the conductive pattern.

Abstract translation: 布线电路板的制造方法包括以下步骤：一体地形成导电图案，与导电图案电连接的镀层引线，以及设置在电镀引线中的调节部分，以调节蚀刻剂穿入导电图案; 并用蚀刻剂蚀刻镀层，同时调节部分调节蚀刻剂穿入导电图案。

公开(公告)号：US20090204934A1

公开(公告)日：2009-08-13

申请号：US12030667

申请日：2008-02-13

Applicant: Yu-Sen Lin

Inventor： Yu-Sen Lin

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H05K1/0245 ,  H05K1/0248 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09263

Abstract: A method for compensating length of differential pair and a method for calculating compensation length of the zigzagging type delay line thereof are provided. The method for calculating compensation length of the zigzagging type delay line includes following steps. The quantity A of hypotenuse and the quantity B of bends of the zigzagging type delay line are counted. The width W of the zigzagging type delay line is measured. The height S1 of the parallel line segment of the zigzagging type delay line is measured. An equation L diff = A ( 2 - 1 )  ( S 1 - ( 5  W / 6 ) ) + B  { [ W 5  ( 1 + 2 ) ] 2 + [ W 5 ] 2 - [ W 5  ( 1 + 2 ) ] } is calculated for calculating the compensation length Ldiff of the zigzagging type delay line.

公开(公告)号：US20090145973A1

公开(公告)日：2009-06-11

申请号：US12348364

申请日：2009-01-05

Applicant: Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

Inventor： Mukta G. Farooq ,  Benjamin V. Fasano ,  Jason L. Frankel ,  Harvey C. Hamel ,  Suresh D. Kadakia ,  David C. Long ,  Frank L. Pompeo ,  Sudipta K. Ray

IPC: G06K19/06

CPC classification number: G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

Abstract: A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Abstract translation: 防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。

公开(公告)号：US20090102580A1

公开(公告)日：2009-04-23

申请号：US12256332

申请日：2008-10-22

Applicant: Sergey V. Uchaykin

Inventor： Sergey V. Uchaykin

IPC: H03H7/00

CPC classification number: H01P1/2039 ,  H01P1/227 ,  H05K1/0224 ,  H05K1/0234 ,  H05K1/09 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09318 ,  H05K2201/09663

Abstract: An electronic filtering device includes continuous trace on a dielectric substrate and a dissipation layer communicatively coupled to the trace. The dissipation layer may include disconnected metal particles, which may be embedded in a substrate, for example in an epoxy. The continuous trace may be meandering, for example crenulated, coil or spiral signal path. At least a second continuous trace may be spaced from the first by the substrate, and conductively coupled by a via. The electronic filtering device may be used in one or more printed circuit boards (PCBs) that form stages of an input/output system.

Abstract translation: 电子滤波装置包括电介质基底上的连续迹线和与迹线通信耦合的耗散层。 耗散层可以包括分离的金属颗粒，其可以嵌入在基底中，例如环氧树脂中。 连续的迹线可能是曲折的，例如曲线，线圈或螺旋信号路径。 至少第二连续迹线可以与第一连续迹线间隔开，并且由通孔导电耦合。 电子滤波装置可以用于形成输入/输出系统阶段的一个或多个印刷电路板（PCB）中。

公开(公告)号：US07523246B2

公开(公告)日：2009-04-21

申请号：US11681390

申请日：2007-03-02

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/42

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory system includes a first signal line to carry a first signal that enters the module at a first end of the first signal line and a second signal line to carry a second signal that enters the module at a first end of the second signal line. The module includes a first memory device disposed on a first side of the module and a second memory module disposed on a second side of the module positioned opposite to the first side. The first memory device and the second memory device are connected to the first signal line and the second signal line. The first signal and the second signal traverse alongside each other to arrive in turn at the first memory device and the second memory device. The system may include a controller that provides the first signal and the second signal.

Abstract translation: 存储器系统包括：第一信号线，用于承载在第一信号线的第一端进入模块的第一信号;以及第二信号线，用于承载在第二信号线的第一端进入模块的第二信号。 模块包括设置在模块的第一侧上的第一存储器件和设置在与第一侧相对定位的模块的第二侧上的第二存储器模块。 第一存储器件和第二存储器件连接到第一信号线和第二信号线。 第一信号和第二信号彼此并行地依次移动以在第一存储器件和第二存储器件上依次进入。 该系统可以包括提供第一信号和第二信号的控制器。

公开(公告)号：US07519757B2

公开(公告)日：2009-04-14

申请号：US11691406

申请日：2007-03-26

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/42

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

Abstract translation: 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US20090086522A1

公开(公告)日：2009-04-02

申请号：US12239900

申请日：2008-09-29

Applicant: Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

Inventor： Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

IPC: G11C5/06 ,  H05K1/18 ,  H05K7/00

CPC classification number: G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract translation: 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

公开(公告)号：US07402756B2

公开(公告)日：2008-07-22

申请号：US11402000

申请日：2006-04-12

Applicant: Hiroji Hoshino

Inventor： Hiroji Hoshino

IPC: H05K1/02 ,  H05K7/06

CPC classification number: H05K1/118 ,  H05K1/117 ,  H05K2201/09263 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/09727 ,  H05K2203/1572

Abstract: A double-sided flexible circuit board with enhanced rigidity of terminals by using copper foil on an opposite side of the circuit board is provided. The flexible circuit board having wiring patterns P for connecting terminals on each of a front surface A and a back surface B of its periphery, includes: terminal patterns with linear-planar-shaped traces, the traces of which are equally spaced and disposed on the peripheries of each of the front surface and the back surface of the board; and backing patterns with planar-shaped traces, the traces of which are combined with the terminal patterns and bent so that the central portion of the backing pattern is offset from that of the terminal pattern, wherein the traces of the backing patterns are disposed on the corresponding opposite side of the traces of the terminal patterns on the board so as to be positioned overlapping with the traces of the terminal patterns.

Abstract translation: 提供了一种通过在电路板的相对侧使用铜箔来提高端子刚性的双面柔性电路板。 具有用于连接其周边的前表面A和后表面B的端子上的端子的布线图案P的柔性电路板包括：具有线性平面状迹线的端子图案，其迹线相等间隔设置在 板的前表面和后表面中的每一个的周边; 以及具有平面形轨迹的背衬图案，其轨迹与端子图案组合并弯曲，使得背衬图案的中心部分偏离端子图案的中心部分，其中背衬图案的迹线设置在 在板上的端子图案的迹线的对应的相对侧，以便与端子图案的迹线重叠。