公开(公告)号：US20060068582A1

公开(公告)日：2006-03-30

申请号：US10906073

申请日：2005-02-02

Applicant: Thonas Su

Inventor： Thonas Su

IPC: H01L21/50

CPC classification number: H05K1/0237 ,  H05K1/0227 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663 ,  Y10T29/49155

Abstract: A method for decreasing impedance of a power source in a printed circuit board includes: (a) forming a first metal plane over a first layer of the printed circuit board; (b) forming a second metal plane and a third metal plane over a second layer of the printed circuit board; (c) forming a dielectric layer between the first layer and the second layer of the printed circuit board for insulating the first layer from the second layer; and (d) connecting the second metal plane to an electric potential different from an electric potential of the first metal plane and the third metal plane.

Abstract translation: 一种用于降低印刷电路板中的电源的阻抗的方法包括：（a）在印刷电路板的第一层上形成第一金属平面; （b）在所述印刷电路板的第二层上形成第二金属平面和第三金属平面; （c）在印刷电路板的第一层和第二层之间形成绝缘层，用于使第一层与第二层绝缘; 和（d）将第二金属平面连接到不同于第一金属平面和第三金属平面的电位的电位。

公开(公告)号：US20060028806A1

公开(公告)日：2006-02-09

申请号：US11245723

申请日：2005-10-06

Applicant: Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC: H01R9/00

CPC classification number: H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H02M7/003 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K7/1432 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49009 ,  Y10T29/49117 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

公开(公告)号：US06992387B2

公开(公告)日：2006-01-31

申请号：US10602096

申请日：2003-06-23

Applicant: Jennifer A. Hester ,  Yuan-Liang Li ,  Michael M. Desmith ,  David G. Figueroa ,  Dong Zhong

Inventor： Jennifer A. Hester ,  Yuan-Liang Li ,  Michael M. Desmith ,  David G. Figueroa ,  Dong Zhong

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract translation: 根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及 设置在所述第一导电平面和所述第二导电平面之间的电介质。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。

公开(公告)号：US20050039947A1

公开(公告)日：2005-02-24

申请号：US10949290

申请日：2004-09-27

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K1/02 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

Abstract translation: 提供了一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的配线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

公开(公告)号：US06845017B2

公开(公告)日：2005-01-18

申请号：US09957568

申请日：2001-09-20

Applicant: Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett ,  Douglas Maly

Inventor： Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett ,  Douglas Maly

IPC: H01L23/66 ,  H01L25/07 ,  H05K1/02 ,  H05K1/03 ,  H01R9/00

CPC classification number: H01L25/072 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/665 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A DC bus for use in a power module includes a positive DC conductor bus plate parallel with a negative DC conductor bus plate. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract translation: 用于功率模块的DC总线包括与负DC导体总线板平行的正直流导体母线板。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

公开(公告)号：US20040201971A1

公开(公告)日：2004-10-14

申请号：US10408951

申请日：2003-04-08

Inventor： John Thomas Fessler ,  Keith Bryan Hardin ,  Eric Wayne Westerfield

IPC: H05K001/11 ,  H05K007/06

CPC classification number: H05K1/0218 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09772 ,  H05K2201/10689

Abstract: A multi-layer printed circuit board (PCB) routes signal traces on internal signal layer(s) and includes power planes on the two outermost layers. The outer layers are maintained at the same non-ground voltage level, and are electrically connected by a series of vias that circumscribe signal traces on the internal layer(s). With a preferred maximum spacing of one-tenth the wavelength of electromagnetic energy generated by the signal traces, the vias, together with the outer power planes, contain electromagnetic energy within the PCB. One or more of the outer planes may include a second power plane area maintained at a different voltage. The two power plane areas are connected by decoupling capacitors, located proximate underlying signal traces that traverse the two power plane areas.

Abstract translation: 多层印刷电路板（PCB）在内部信号层上传送信号迹线，并且包括两个最外层的电源层。 外层保持在相同的非接地电压电平，并且通过一系列通孔来电连接，这些通孔围绕内层上的信号迹线。 通过由信号迹线产生的电磁能量波长的十分之一的优选最大间距，通孔与外部电源平面在PCB内包含电磁能。 一个或多个外平面可以包括维持在不同电压的第二电源平面区域。 两个电力平面区域通过去耦电容器连接，位于邻近穿过两个电源平面区域的底层信号迹线。

公开(公告)号：US06794744B2

公开(公告)日：2004-09-21

申请号：US10064426

申请日：2002-07-12

Applicant: Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

Inventor： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC: H01L2352

CPC classification number: H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

Abstract translation: 中央处理单元（CPU）的布局结构，其支持两种不同的封装技术，具有包括布局结构的主板和布局方法。 根据本发明的优选实施例的布局结构从上到下顺序地放置了顶部信号层，接地层，具有工作电位区域的功率层和接地电位区域，以及底部焊料层， CPU的信号耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。

公开(公告)号：US20040006407A1

公开(公告)日：2004-01-08

申请号：US10330297

申请日：2002-12-30

Inventor： Chun Hung Chen ,  Hsiu Tzu Chen ,  Yen Chen Chen

IPC: G06F007/00

CPC classification number: H05K1/0262 ,  H05K1/0216 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A layer allocating apparatus for a multi-layer circuit board is disclosed. In a preferred embodiment, the layer allocating apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer. The powerlayer is sliced into a plurality of reference ground areas each is located at somewhere to correspond to signal layout areas of the solder layer, so as to allow signal lines of the component layer and solder layer to take reference to the reference ground areas on the adjacent power layer. The power layer also includes a plurality of power layers each provides different operating voltages, and electrically couples with corresponding power layouts of the solder layer and component layer through vias, thereby enlarging the total area of power planes, so as to provide a table power source and attenuate the ground/bounce effect.

Abstract translation: 公开了一种用于多层电路板的层分配装置。 在优选实施例中，作为组件层，从顶部到底部布置的层分配装置，接地层，功率层和焊料层。 功率层被切割成多个参考接地区域，每个参考接地区域位于与焊料层的信号布局区域相对应的某处，以便允许组件层和焊料层的信号线参考在焊接层​​上的参考接地区域 相邻功率层。 功率层还包括多个功率层，每个功率层各自提供不同的工作电压，并且通过通孔与焊料层和组件层的相应功率布局电耦合，从而扩大电源平面的总面积，从而提供工作台电源 并衰减地面/反弹效果。

公开(公告)号：US06573600B2

公开(公告)日：2003-06-03

申请号：US09817787

申请日：2001-03-27

Applicant: Atsushi Kikuchi ,  Makoto Iijima ,  Yoshihiko Ikemoto ,  Muneharu Morioka ,  Yoshiyuki Kimura

Inventor： Atsushi Kikuchi ,  Makoto Iijima ,  Yoshihiko Ikemoto ,  Muneharu Morioka ,  Yoshiyuki Kimura

IPC: G01R1900

CPC classification number: H05K1/0245 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09345 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multilayer wiring substrate includes differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.

Abstract translation: 多层布线基板包括布置在第一电源平面和第一接地平面之间的第一绝缘层内的差动信号线; 以及放置在第二电源平面和第二接地平面之间的第二绝缘层内的一般信号线。 在多层布线基板中，差分信号线被放置在与具有每个通用信号线的平面不同的平面中，使得不同的平面包括具有差分信号线的第一区域，以及具有第二 电源平面和第二个接地层。 通常的信号线以叠层状态放置在第二区域的垂直方向上，使得每条通用信号线都位于第二电源平面和第二接地面之间。

公开(公告)号：US06535395B2

公开(公告)日：2003-03-18

申请号：US10005464

申请日：2001-12-03

Applicant: Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

Inventor： Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

IPC: H01R1222

CPC classification number: H05K1/141 ,  G06F1/189 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09345 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.