公开(公告)号：US07095625B2

公开(公告)日：2006-08-22

申请号：US10384715

申请日：2003-03-11

Applicant: Kentaro Fukami

Inventor： Kentaro Fukami

IPC: H05K7/10 ,  H05K7/02

CPC classification number: H05K7/1015 ,  H05K1/0292 ,  H05K1/0295 ,  H05K1/116 ,  H05K2201/0979 ,  H05K2201/09954 ,  H05K2203/176

Abstract: An electronic component mounting circuit board for mounting an electronic component, comprises a circuit board, and connection pads provided on the circuit board, the connection pads being formed with a plurality of holes for inserting terminals of the electronic component.

Abstract translation: 一种用于安装电子部件的电子部件安装电路板，包括电路板和设置在电路板上的连接焊盘，连接焊盘形成有用于插入电子部件的端子的多个孔。

公开(公告)号：US07091587B2

公开(公告)日：2006-08-15

申请号：US10820799

申请日：2004-04-09

Applicant: Yusuke Sato ,  Kenji Koyama ,  Toshihiro Miura ,  Toshihiko Kyogoku

Inventor： Yusuke Sato ,  Kenji Koyama ,  Toshihiro Miura ,  Toshihiko Kyogoku

IPC: H01L23/02

CPC classification number: H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L25/165 ,  H01L2223/6655 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/0205 ,  H03F1/0283 ,  H03F3/195 ,  H03F2200/111 ,  H03F2200/18 ,  H03F2200/408 ,  H03F2200/451 ,  H05K1/0263 ,  H05K1/115 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electrode on a main surface of a module board, to which an emitter electrode of a semiconductor chip which includes a switching element of a power supply control circuit that supplies a power supply voltage to amplifier circuit parts of a power module of a digital cellular phone, is electrically connected to a wiring in an internal layer of the module board through a plurality of via holes. Further, the wiring is electrically connected to an electrode for the supply of the power supply voltage, which is provided on a back surface of the module board. Accordingly, an output characteristic of the semiconductor device is improved.

Abstract translation: 模块板的主表面上的电极，半导体芯片的发射极电极包括电源控制电路的开关元件，电源控制电路将电源电压提供给数字蜂窝电话的电源模块的放大器电路部分 通过多个通孔电连接到模块板的内层中的布线。 此外，布线电连接到设置在模块板的背面上的用于提供电源电压的电极。 因此，提高了半导体器件的输出特性。

公开(公告)号：US07075185B2

公开(公告)日：2006-07-11

申请号：US10940100

申请日：2004-09-14

Applicant: Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

Inventor： Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

IPC: H01L23/48

CPC classification number: H01L23/5384 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract translation: 公开了一种用于从旁路电容器焊盘排列多层衬底中的通孔的方法。 方法的一个实施例可以包括布置在多层基板的第一表面上与旁路电容器接地垫间隔开的旁路电容器功率垫，将多个电源通孔从旁路电容器功率垫路由到与第二再分布层间隔开的第一再分配层 并且将多个接地通孔从旁路电容器接地焊盘路由到第一再分布层。 该方法还可以包括将第一再分配层处的多个接地通孔点动到多个电源通孔以提供电源和接地通孔图案，并将电源和接地通孔从第一再分配层路由到间隔开的第二再分配层 基于通过图案的功率和接地的第一再分配层。

公开(公告)号：US20050156319A1

公开(公告)日：2005-07-21

申请号：US10515511

申请日：2003-04-18

Applicant: Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

Inventor： Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

IPC: H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H01L23/48

CPC classification number: H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis. In a preferred embodiment, the shape of these aligned conductive tracks looks like a disk or an annular ring and four vias are used to connect two adjacent conductive layers. These four vias are symmetrically disposed on each of said conductive track. The position of the vias between a first and a second adjacent conductive layers and between a second and a third adjacent conductive layers forms an angle of 45° according to z axis.

Abstract translation: 公开了一种适于通过电子设备载体的导电层传输高频信号或高强度电流的堆叠通孔结构（200）。 叠置的通孔结构包括属于由电介质层（120）分开的根据z轴对准的三个相邻导电层（110a，110b，110c）的至少三个导电轨道（205a，205b，205c）。 这些导电轨道之间的连接通过在每个导电层之间的至少两个通孔（210,215）进行。 连接到导电轨道的一侧的通孔布置成使得它们不与根据z轴连接到另一侧的那些对准。 在优选实施例中，这些对准的导电轨迹的形状看起来像盘或环形环，并且四个通孔用于连接两个相邻的导电层。 这四个通孔对称地设置在每个导电轨道上。 在第一和第二相邻导电层之间以及第二和第三相邻导电层之间的通孔的位置根据z轴形成45°的角度。

公开(公告)号：US20050139391A1

公开(公告)日：2005-06-30

申请号：US10977192

申请日：2004-10-29

Applicant: Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

Inventor： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

IPC: H01L23/498 ,  H01L23/66 ,  H01P3/08 ,  H05K1/02 ,  H05K7/06

CPC classification number: H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

公开(公告)号：US20050130463A1

公开(公告)日：2005-06-16

申请号：US10968066

申请日：2004-10-20

Applicant: Hiromichi Watanabe ,  Yoshifumi Fukatsu ,  Yasuo Nishioka

Inventor： Hiromichi Watanabe ,  Yoshifumi Fukatsu ,  Yasuo Nishioka

IPC: H01R4/18 ,  H01R12/00 ,  H01R43/16 ,  H05K3/30

CPC classification number: H01R12/58 ,  H05K3/308 ,  H05K2201/0979 ,  H05K2201/1059 ,  H05K2201/10787

Abstract: A pressfit terminal is to be inserted into a through hole defined in a substrate for electrically contacting with the through hole. The pressfit terminal includes a terminal main body and at least three protrusion portions. The at least three protrusion portions protrude outwardly from a surface of the terminal main body. At least part of the protrusion portions are arranged at intervals in a direction intersecting with an insertion direction of the terminal main body.

Abstract translation: 压接端子被插入到限定在基板中的通孔中，以与通孔电接触。 压配端子包括端子主体和至少三个突出部。 所述至少三个突起部从所述端子主体的表面向外突出。 突出部的至少一部分在与端子主体的插入方向相交的方向上间隔地配置。

公开(公告)号：US20050011674A1

公开(公告)日：2005-01-20

申请号：US10620733

申请日：2003-07-16

Applicant: Modest Oprysko ,  Lei Shan ,  Jeannine Trewhella

Inventor： Modest Oprysko ,  Lei Shan ,  Jeannine Trewhella

IPC: H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K7/06

CPC classification number: H05K1/113 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: An integrated circuit arrangement or package includes a set of contact pads arranged in a pattern and a multi-layer conductive structure, which electrically connects the set of contact pads to at least one signal line. The conductive structure provides impedance matching between the pads and the at least one signal line.

Abstract translation: 集成电路布置或封装包括以图案布置的一组接触焊盘和多层导电结构，其将该组接触焊盘电连接到至少一个信号线。 导电结构提供焊盘和至少一个信号线之间的阻抗匹配。

公开(公告)号：US20050006140A1

公开(公告)日：2005-01-13

申请号：US10478295

申请日：2002-05-18

Applicant: Dietmar Birgel ,  Sergej Lopatin

Inventor： Dietmar Birgel ,  Sergej Lopatin

IPC: H05K3/34 ,  H01L23/12 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28 ,  H05K3/32 ,  H05K3/36

CPC classification number: H05K3/363 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/114 ,  H05K3/28 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/09063 ,  H05K2201/0979 ,  H05K2201/10666 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655

Abstract: A circuit board having, between the circuit board and a component arranged thereon, an electrical and mechanical connection of high mechanical-load-bearing ability. The circuit board includes at least one internally situated conductor path, a first insulating layer arranged on a first surface of the circuit board, a second insulating layer arranged on a second surface of the circuit board, a first contact location at which the conductor path is accessible, a second contact location, at which the conductor path is accessible through a bore passing completely through the circuit board, and an electronic component arranged on the first surface. The component has a first contact surface, which is connected with the first contact location by solder or electrically conductive adhesive, and a second contact surface which is connected with the second contact location by solder or adhesive.

Abstract translation: 在电路板和布置在其上的部件之间具有高机械承载能力的电气和机械连接的电路板。 所述电路板包括至少一个内部定位的导体路径，布置在所述电路板的第一表面上的第一绝缘层，布置在所述电路板的第二表面上的第二绝缘层，所述导体路径为 可接近的第二接触位置，导体路径可以通过完全穿过电路板的孔访问，以及布置在第一表面上的电子部件。 该部件具有通过焊料或导电粘合剂与第一接触位置连接的第一接触表面，以及通过焊料或粘合剂与第二接触位置连接的第二接触表面。

公开(公告)号：US20040238970A1

公开(公告)日：2004-12-02

申请号：US10868066

申请日：2004-06-16

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： David J. Alcoe

IPC: H01L023/48

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  H01L2224/0401

Abstract: A circuitized substrate which utilizes an underlying conductive layer coupled to a pad on the substrate to assure a reinforced pad which will not be damaged or removed from the substrate when subjected to a significant load. Two or more pads can be similarly provided and coupled to the conductive layer, e.g., the layer being a common (ground) layer. An information handling system (e.g., a personal computer) utilizing the substrate is also provided.

Abstract translation: 电路化基板，其利用与基板上的焊盘耦合的下层导电层，以确保在经受显着载荷时不会损坏或从基板移除的加强垫。 可以类似地提供两个或更多个焊盘并耦合到导电层，例如该层是公共（接地）层。 还提供了利用该基板的信息处理系统（例如个人计算机）。

公开(公告)号：US06820328B2

公开(公告)日：2004-11-23

申请号：US10328337

申请日：2002-12-23

Applicant: Tina P. Barcley

Inventor： Tina P. Barcley

IPC: H05K330

CPC classification number: H05K1/0206 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0209 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2201/0979 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method removes heat from a densely packed electronic assemblage. Densely packed electronic assemblage has a substrate medium for supporting at least one heat generating component and means for reducing the temperature of the at least one heat generating component. A heat sink cooperates with the heat removing element for reducing heat of the heat generating component by absorbing heat from the heat generating component.