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    Nonvolatile Memory Device
    2.
    发明申请
    Nonvolatile Memory Device 失效
    非易失性存储器件

    公开(公告)号：US20130087847A1

    公开(公告)日：2013-04-11

    申请号：US13656120

    申请日：2012-10-19

    Applicant: HYNIX SEMICONDUCTOR INC.

    Inventor： Yun Kyoung Lee

    IPC: H01L29/792

    CPC classification number: H01L29/792 ,  H01L27/11568 ,  H01L29/66833

    Abstract: Patterns of a nonvolatile memory device include a semiconductor substrate that defines active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layers is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.

    Abstract translation: 非易失性存储器件的图案包括限定沿纵向延伸的有源区的半导体衬底，形成在有源区之间的隔离结构，形成在有源区上的隧道绝缘层，形成在隧道绝缘层上的电荷陷阱层， 形成在所述电荷陷阱层和所述隔离结构上的第一电介质层，其中所述第一电介质层沿着横向延伸;形成在所述第一介电层上的控制栅极层，其中所述控制栅极层沿着所述横向方向延伸， 以及第二电介质层，其沿着横向方向形成在所述控制栅极层的侧壁上并且耦合到所述第一介电层。

    TEMPERATURE DETECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARTUS
    3.
    发明申请
    TEMPERATURE DETECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARTUS 有权
    半导体存储器温度检测电路

    公开(公告)号：US20130083616A1

    公开(公告)日：2013-04-04

    申请号：US13664971

    申请日：2012-10-31

    Applicant: Hynix Semiconductor Inc.

    Inventor： Je-Yoon Lee ,  Jong Chern Lee

    IPC: G11C7/04

    CPC classification number: G11C7/04 ,  G11C11/406 ,  G11C11/40626

    Abstract: A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.

    Abstract translation: 半导体存储装置的温度检测电路包括固定周期振荡器，温度可变信号发生单元和计数单元。 振荡器被配置为当启用使能信号时产生固定周期振荡器信号。 温度可变信号发生单元被配置为当使能信号被使能时，产生其使能间隔基于温度变化而变化的温度可变信号。 计数单元被配置为在温度可变信号的使能间隔期间对振荡器信号进行计数，以产生温度信息信号。

    CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    充电陷阱型非易失性存储器件及其制造方法

    公开(公告)号：US20130078794A1

    公开(公告)日：2013-03-28

    申请号：US13682276

    申请日：2012-11-20

    Applicant: Hynix Semiconductor Inc.

    Inventor： Cha-Deok DONG

    IPC: H01L29/40

    CPC classification number: H01L29/401 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

    Abstract: There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.

    Abstract translation: 提供了一种电荷阱型非易失性存储器件及其制造方法，该电荷阱型非易失性存储器件包括：在衬底上形成的隧道绝缘层; 形成在隧道绝缘层上的电荷陷阱层，电荷陷阱层包括电荷陷阱多晶硅薄层和电荷陷阱氮化物基层; 形成在电荷陷阱层上的电荷阻挡层; 形成在电荷阻挡层上的栅电极; 以及形成在电荷陷阱层的侧壁上的氧化物基间隔物，并且被提供以隔离电荷陷阱层。

    PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND FABRICATION METHOD THEREOF
    5.
    发明申请
    PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND FABRICATION METHOD THEREOF 有权
    具有减少干扰的相变存储器件及其制造方法

    公开(公告)号：US20130071985A1

    公开(公告)日：2013-03-21

    申请号：US13676433

    申请日：2012-11-14

    Applicant: Hynix Semiconductor Inc.

    Inventor： Jang Uk LEE

    IPC: H01L49/02

    CPC classification number: H01L28/20 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes.

    Abstract translation: 提出了能够减少相邻PRAM存储单元之间的干扰的相变存储器件和制造方法。 相变存储器件包括字线，加热电极，层间绝缘层和相变线。 字线形成在半导体衬底上并且以恒定的空间平行延伸。 加热电极与多条字线电连接。 层间绝缘层绝热加热电极。 相变线在与字线正交的方向上延伸并且电连接到加热电极。 在字线之间的层间绝缘层的表面上形成曲线，使得相邻加热电极之间的相变层的有效长度大于相邻加热电极之间的物理距离。

    SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING COATING FILM AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING COATING FILM AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    具有涂膜的半导体封装用基板及其制造方法

    公开(公告)号：US20130029458A1

    公开(公告)日：2013-01-31

    申请号：US13627312

    申请日：2012-09-26

    Applicant: HYNIX SEMICONDUCTOR INC.

    Inventor： Woong Sun LEE

    IPC: H01L21/60

    CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/247 ,  H05K3/3457 ,  H05K2201/035 ,  H05K2201/09436 ,  H01L2924/00

    Abstract: A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process.

    Abstract translation: 用于半导体封装的衬底包括设置在绝缘层的一个表面上的球形区域。 在绝缘层的表面上施加阻焊剂，同时露出球场。 将涂膜施加在球面的暴露表面上。 涂膜包括具有金属颗粒的高分子化合物。 在其上形成有涂膜的球面的基板中，不需要使基板进行UBM形成工艺。

    Method for manufacturing capacitor of semiconductor device
    9.
    发明申请
    Method for manufacturing capacitor of semiconductor device 失效
    制造半导体器件电容器的方法

    公开(公告)号：US20040266125A1

    公开(公告)日：2004-12-30

    申请号：US10721093

    申请日：2003-11-26

    Applicant: Hynix Semiconductor Inc.

    Inventor： Jong Han Shin ,  Sang Ick Lee

    IPC: H01L021/20

    CPC classification number: H01L28/65 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/75

    Abstract: The present invention discloses method for manufacturing capacitor of semiconductor device wherein a bonding layer is exposed via etch-back process without using a contact hole mask. In accordance with the method of the present invention, an interlayer insulating film, a bonding layer and a hard mask layer are sequentially formed on a semiconductor substrate. The hard mask layer, the bonding layer and the interlayer insulating film are then etched to form a storage electrode contact hole. The storage electrode contact hole is partially filled to form a storage electrode contact plug and the remaining portion is filled with a barrier metal layer pattern. The hard mask layer is then removed and a storage electrode contacting the barrier metal layer pattern is then formed on the bonding layer.

    Precharge apparatus in semiconductor memory device and precharge method using the same
    10.
    发明申请
    Precharge apparatus in semiconductor memory device and precharge method using the same 审中-公开
    半导体存储装置中的预充电装置及使用其的预充电方法

    公开(公告)号：US20040264275A1

    公开(公告)日：2004-12-30

    申请号：US10742313

    申请日：2003-12-19

    Applicant: HYNIX SEMICONDUCTOR INC.

    Inventor： Ja Seung Gou

    IPC: G11C007/00

    CPC classification number: G11C7/1066 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4094

    Abstract: Disclosed is a precharge apparatus in a semiconductor memory device and a precharge method using the same. The precharge apparatus includes a memory array in which a plurality of memory banks are divided into at least two memory groups, and a precharge all command decoder to generate at least two precharge signals according to a precharge command signal and an address signal, wherein the at least two precharge signals are each output with a time lag according to a control signal to precharge the ate least two memory groups with a time lag. Therefore, the peak current is distributed to reduce the power bouncing.

    Abstract translation: 公开了一种半导体存储器件中的预充电装置和使用该预充电装置的预充电方法。 预充电装置包括其中多个存储体被划分为至少两个存储器组的存储器阵列和根据预充电命令信号和地址信号产生至少两个预充电信号的预充电全命令解码器，其中， 至少两个预充电信号各自根据控制信号以时间滞后的方式输出，以便以至少两个存储器组以时间延迟。 因此，分配峰值电流以减少功率跳动。

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