公开(公告)号：US10236225B2

公开(公告)日：2019-03-19

申请号：US15944830

申请日：2018-04-04

Applicant: Applied Materials, Inc.

Inventor： Yoichi Suzuki ,  Michael Wenyoung Tsiang ,  Kwangduk Douglas Lee ,  Takashi Morii ,  Yuta Goto

IPC: H01L21/66 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/324 ,  H01L21/02 ,  H01L21/67 ,  H01L21/677 ,  C23C16/46

Abstract: The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.

公开(公告)号：US20220130665A1

公开(公告)日：2022-04-28

申请号：US17077926

申请日：2020-10-22

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung Tsiang ,  Abdul Aziz Khaja ,  Li-Qun Xia ,  Kevin Hsiao ,  Liangfa Hu ,  Yayun Cheng

IPC: H01L21/02 ,  H01L21/311 ,  C23C16/26

Abstract: Exemplary processing methods may include forming a plasma of a deposition precursor in a processing region of a semiconductor processing chamber. The methods may include adjusting a variable capacitor within 20% of a resonance peak. The variable capacitor may be coupled with an electrode incorporated within a substrate support on which a substrate is seated. The methods may include depositing a material on the substrate.

公开(公告)号：US10483282B2

公开(公告)日：2019-11-19

申请号：US16267151

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung Tsiang ,  Praket P. Jha ,  Xinhai Han ,  Bok Hoen Kim ,  Sang Hyuk Kim ,  Myung Hun Ju ,  Hyung Jin Park ,  Ryeun Kwan Kim ,  Jin Chul Son ,  Saiprasanna Gnanavelu ,  Mayur G. Kulkarni ,  Sanjeev Baluja ,  Majid K. Shahreza ,  Jason K. Foster

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/505 ,  C23C16/52 ,  C23C16/40 ,  H01L27/11582 ,  H01L29/06 ,  H01L21/3115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/768 ,  C23C16/455 ,  H01L21/311 ,  H01L21/3105

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

公开(公告)号：US09947599B2

公开(公告)日：2018-04-17

申请号：US15492428

申请日：2017-04-20

Applicant: Applied Materials, Inc.

Inventor： Yoichi Suzuki ,  Michael Wenyoung Tsiang ,  Kwangduk Douglas Lee ,  Takashi Morii ,  Yuta Goto

IPC: H01L21/66 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/324 ,  H01L21/02 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L22/20 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/324 ,  H01L21/67098 ,  H01L21/67109 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67742 ,  H01L22/12

Abstract: The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.

公开(公告)号：US09816187B2

公开(公告)日：2017-11-14

申请号：US15278455

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Wenyoung Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik ,  Ganesh Balasubramanian

IPC: G01N21/00 ,  C23C16/52 ,  G01B11/06 ,  H01L21/00 ,  H01L21/687 ,  H01L21/67 ,  C23C16/509 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  G01N21/55 ,  G01N21/65 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/45565 ,  C23C16/4557 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  G01N2201/1222 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

公开(公告)号：US12300554B2

公开(公告)日：2025-05-13

申请号：US18349930

申请日：2023-07-10

Applicant: Applied Materials, Inc.

Inventor： Mandar B. Pandit ,  Man-Ping Cai ,  Wenhui Li ,  Michael Wenyoung Tsiang ,  Praket Prakash Jha ,  Jingmin Leng

IPC: H01L21/66 ,  C23C16/40 ,  C23C16/52 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.

公开(公告)号：US11898249B2

公开(公告)日：2024-02-13

申请号：US18108989

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Wenyoung Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward W. Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik ,  Ganesh Balasubramanian

IPC: C23C16/52 ,  G01B11/06 ,  H01L21/687 ,  H01L21/67 ,  C23C16/509 ,  G01N21/55 ,  G01N21/65 ,  H01L21/00 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/458 ,  C23C16/4557 ,  C23C16/45565 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687 ,  G01N2201/1222

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

公开(公告)号：US11133177B2

公开(公告)日：2021-09-28

申请号：US16673943

申请日：2019-11-04

Applicant: Applied Materials, Inc.

Inventor： Martin Jay Seamons ,  Michael Wenyoung Tsiang ,  Jingmei Liang

IPC: H01L21/02 ,  C23C16/50 ,  C23C16/40 ,  C23C16/04

Abstract: Embodiments described herein generally related to methods for forming a flowable low-k dielectric layer over a trench formed on a surface of a patterned substrate. The methods include delivering a silicon and carbon containing precursor into a substrate processing region of a substrate processing chamber for a first period of time and a second period of time, flowing an oxygen-containing precursor into a remote plasma region of a plasma source while igniting a remote plasma to form a radical-oxygen precursor, flowing the radical-oxygen precursor into the substrate processing region at a second flow rate after the first period of time has elapsed and during the second period of time, and exposing the silicon and carbon containing dielectric precursor to electromagnetic radiation for a third period of time after the second period of time has elapsed.

公开(公告)号：US11060189B2

公开(公告)日：2021-07-13

申请号：US16464892

申请日：2017-12-18

Applicant: Applied Materials, Inc.

Inventor： Michael Wenyoung Tsiang ,  Praket P. Jha ,  Deenesh Padhi

IPC: H01L21/02 ,  C23C16/44 ,  C23C16/24 ,  C23C16/40 ,  C23C16/505 ,  H01J37/32

Abstract: Implementations of the present disclosure provide methods for processing substrates in a processing chamber. In one implementation, the method includes (a) depositing a dielectric layer on a first substrate at a first chamber pressure using a first high-frequency RF power, (b) depositing sequentially a dielectric layer on N substrates subsequent to the first substrate at a second chamber pressure, wherein N is an integral number of 5 to 10, and wherein depositing each substrate of N substrates comprises using a second high-frequency RF power that has a power density of about 0.21 W/cm2 to about 0.35 W/cm2 lower than that of the first high-frequency RF power, (c) performing a chamber cleaning process without the presence of a substrate, and (d) repeating (a) to (c).

公开(公告)号：US11699623B2

公开(公告)日：2023-07-11

申请号：US17070751

申请日：2020-10-14

Applicant: Applied Materials, Inc.

Inventor： Mandar B. Pandit ,  Man-Ping Cai ,  Wenhui Li ,  Michael Wenyoung Tsiang ,  Praket Prakash Jha ,  Jingmin Leng

IPC: H01L21/66 ,  H01L21/02 ,  C23C16/52 ,  C23C16/40 ,  H01L21/67

CPC classification number: H01L22/20 ,  C23C16/401 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/67288

Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.