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公开(公告)号:US20250157970A1
公开(公告)日:2025-05-15
申请号:US18932755
申请日:2024-10-31
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Kung-Tzu Tu , Gwo-Shyan Sheu , Hsin-Hao Huang , Kuo-Liang Huang , Pei-Wen Wang , Yu-Chen Ma
IPC: H01L23/00 , H01L23/498
Abstract: A flip chip structure includes a circuit board and a chip. The circuit board includes first inner leads and second inner leads, each of the first inner leads has a first bonding portion, each of the second inner leads has a second bonding portion and a connecting segment. An included angle exists between the second bonding portion and the connecting segment, and an included angle exists between center lines of the first and second bonding portions. The chip includes first bumps and second bumps, and an included angle exists between center lines of the first and second bumps. Each of the first bumps is bonded to the first bonding portion, and each of the second bumps is bonded to the second bonding portion and the connecting segment to avoid bonding shift between the inner leads and the bumps or lessen bonding shift.
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公开(公告)号:US20230044345A1
公开(公告)日:2023-02-09
申请号:US17848481
申请日:2022-06-24
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Yu-Chen Ma , Pei-Wen Wang , Hsin-Hao Huang , Gwo-Shyan Sheu
IPC: H05K1/18 , H05K1/02 , H01L23/498
Abstract: A layout structure of flexible circuit board includes a flexible substrate, a circuit layer, a flip-chip element and an anti-stress circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. Bonding circuits and transmission circuits of the circuit layer are disposed on the chip mounting area and the circuit area respectively. The flip-chip element is disposed on the chip mounting area and includes bumps and a chip having a long side margin and conductive pads, the bumps are provided to connect the conductive pads and the bonding circuits. Anti-stress circuits of the anti-stress circuit layer are disposed on the chip mounting area and parallel to the long side margin of the chip, and the bumps are located between the anti-stress circuits and the long side margin of the chip.
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公开(公告)号:US20240389224A1
公开(公告)日:2024-11-21
申请号:US18544631
申请日:2023-12-19
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Kung-Tzu Tu , Gwo-Shyan Sheu , Kuo-Liang Huang , Pei-Wen Wang , Yu-Chen Ma , Chia-Hsin Yen
IPC: H05K1/02
Abstract: A thin film circuit board includes a substrate and a thermal conductive film which is adhered to the substrate and includes a first conductive portion, a second conductive portion and a third conductive portion. The thermal conductive film is designed to be polygonal and non-rectangular in order to reduce stress generated in the substrate and the thermal conductive film and protect the thin film circuit board from warpage.
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公开(公告)号:US20240074041A1
公开(公告)日:2024-02-29
申请号:US18234642
申请日:2023-08-16
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Gwo-Shyan Sheu , Kuo-Liang Huang , Hsin-Hao Huang , Pei-Wen Wang , Yu-Chen Ma
CPC classification number: H05K1/0268 , H05K1/111
Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.
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公开(公告)号:US20230163061A1
公开(公告)日:2023-05-25
申请号:US17975692
申请日:2022-10-28
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Yu-Chen Ma , Pei-Wen Wang , Hsin-Hao Huang , Gwo-Shyan Sheu
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49838 , H01L23/4985 , H01L24/16 , H01L24/32 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L24/73 , H01L2224/26175
Abstract: In a semiconductor package, flow guiding strips are provided on a guiding area of a flexible substrate to separate a chip and the flexible substrate such that a filling material flowing between the chip and the flexible substrate can squeeze out the air between the chip and the flexible substrate to improve the reliability of the semiconductor package.
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公开(公告)号:US20250159801A1
公开(公告)日:2025-05-15
申请号:US18910291
申请日:2024-10-09
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Kung-Tzu Tu , Gwo-Shyan Sheu , Hsin-Hao Huang , Kuo-Liang Huang , Pei-Wen Wang , Yu-Chen Ma
Abstract: A flexible circuit board includes a flexible substrate, a first circuit and a second circuit. The first circuit is provided on a first area defined on the top surface and includes a first input terminal and a first output terminal. The first input terminal is adjacent to a bottom side of the top surface and the first output terminal is adjacent to a top side of the top surface. The second circuit is provided on a second area defined on the top surface and includes a second input terminal and a second output terminal. The second input terminal is adjacent to the top side of the top surface and the second output terminal is adjacent to the bottom side of the top surface.
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公开(公告)号:US20250071889A1
公开(公告)日:2025-02-27
申请号:US18789994
申请日:2024-07-31
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor: Kung-Tzu Tu , Gwo-Shyan Sheu , Hsin-Hao Huang , Pei-Wen Wang , Yu-Chen Ma , Erh-Shun Chuang
Abstract: A flexible circuit board includes a flexible substrate, a chip, a first test area, first test pads and a circuit layer connected to the chip and the first test pads. A working area and a non-working area are defined on an upper surface of the flexible substrate. The chip is disposed on the working area, the first test area is located within the non-working area and between a third edge and the working area, the first test pads are arranged on the first test area. Flexible circuit boards with different sizes can have the first test area with the same size and can be tested using a probe card with the same specification to lower testing cost.
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