公开(公告)号：US09508676B1

公开(公告)日：2016-11-29

申请号：US14848439

申请日：2015-09-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Fu-Yen Ho ,  Yen-Ting Chen

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L21/50 ,  H01L23/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/14179 ,  H01L2224/16245 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/165

Abstract: A semiconductor package structure having hollow chamber includes a bottom substrate having a bottom baseboard and a bottom metal layer formed on a disposing area of the bottom baseboard, a connection layer formed on the bottom metal layer, and a top substrate. The bottom metal layer has at least one corner having a first and a second outer lateral surface, and an outer connection surface. A first extension line is formed from a first extreme point of the first outer lateral surface, and a second extension line is formed from a second extreme point of the second outer lateral surface. A first exposing area of the bottom baseboard is formed by connecting the first and second extreme points and a cross point of the first and second extreme points. The top substrate connects to the connection layer to form a hollow chamber between the top and bottom substrates.

Abstract translation: 具有中空室的半导体封装结构包括：底部基板，具有形成在底部基板的设置区域上的底部基板和底部金属层，形成在底部金属层上的连接层和顶部基板。 底部金属层具有至少一个具有第一和第二外侧表面的角部和外部连接表面。 第一延伸线由第一外侧表面的第一极点形成，第二延伸线由第二外侧表面的第二极限点形成。 通过连接第一极点和第二极值点以及第一和第二极值点的交叉点来形成底部基板的第一暴露区域。 顶部衬底连接到连接层，以在顶部和底部衬底之间形成中空室。

公开(公告)号：US20160318756A1

公开(公告)日：2016-11-03

申请号：US14736328

申请日：2015-06-11

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Fu-Yen Ho ,  Yen-Ting Chen

IPC: B81C1/00

CPC classification number: H01L23/10 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50

Abstract: A process for manufacturing a semiconductor package having a hollow chamber includes providing a bottom substrate having a bottom plate, a ring wall and a slot, wherein the ring wall and the bottom plate form the slot; forming an under ball metallurgy layer on a surface of the ring wall;bumping a plurality of solder balls on a surface of the under ball metallurgy layer, each of the solder balls comprises a diameter, wherein a spacing is spaced apart between two adjacent solder balls; performing reflow soldering to the solder balls for making the solder balls melting and interconnecting to form a connection layer; connecting a top substrate to the bottom substrate, wherein the lot of the bottom substrate is sealed by the top substrate to form a hollow chamber used for accommodating an electronic device.

Abstract translation: 在球形冶金层的表面上碰撞多个焊球，每个焊球包括直径，其中间隔在两个相邻的焊球之间间隔开; 对所述焊球进行回流焊接，以使所述焊球熔化并互连以形成连接层; 将顶部基板连接到底部基板，其中底部基板的批次被顶部基板密封以形成用于容纳电子设备的中空室。

公开(公告)号：US20130256882A1

公开(公告)日：2013-10-03

申请号：US13903447

申请日：2013-05-28

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

IPC: H01L23/58 ,  H01L23/498

CPC classification number: H01L23/58 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer.

公开(公告)号：US20130252374A1

公开(公告)日：2013-09-26

申请号：US13893620

申请日：2013-05-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Yung-Wei Hsieh ,  Bo-Shiun Jiang

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.

Abstract translation: 半导体封装方法包括提供具有多个焊盘的衬底，每个焊盘包括具有多个第一导电接触区域和多个第一非导电接触区域的第一耦合表面; 在基板上形成具有抗解离功能的导电凝胶，所述可导电凝胶包括多个导电颗粒和多个抗分解物质; 将芯片安装在基板上，所述芯片包括多个含铜凸块，每个含铜凸块包括环表面和具有多个第二导电接触区域和多个第二非导电性接触区域的第二耦合表面 接触区域，其中所述导电颗粒与所述第一导电接触区域和所述第二导电接触区域电连接，所述抗分解物质与所述第二非导电接触区域接触，并且所述环形表面被所述反 - 解离物质

公开(公告)号：US20130249089A1

公开(公告)日：2013-09-26

申请号：US13893623

申请日：2013-05-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05666 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2224/05552

Abstract: A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.

Abstract translation: 制造细间距凸块的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成含钛金属层，其中所述含钛金属层包括多个第一区和多个第二区; 在含钛金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口槽; 在开口槽处形成多个铜凸块，其中每个铜凸块包括第一顶表面和环表面; 加热光致抗蚀剂层以形成多个主体部分和多个可移除部分; 蚀刻光致抗蚀剂层; 以及移除所述第二区域以使得所述第一区域中的每一个能够形成具有轴承部分和延伸部分的凸起下金属层。