公开(公告)号：US20100294553A1

公开(公告)日：2010-11-25

申请号：US12851807

申请日：2010-08-06

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. The core circuit board has at least one metal layer, and the core circuit board has at least one conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the core circuit board and connected to the metal layer. At least one dielectric layer covers the core circuit board, and the dielectric layer has an embedded hole. At least one wiring layer covers the dielectric layer and connected to the embedded hole.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括芯电路板，至少一个嵌入式电容器，至少一个电介质层和至少一个布线层。 核心电路板具有至少一个金属层，并且核心电路板具有连接到金属层的至少一个导电通孔。 至少一个嵌入式电容器嵌入在核心电路板中并连接到金属层。 至少一个电介质层覆盖核心电路板，电介质层具有嵌入孔。 至少一个布线层覆盖电介质层并连接到嵌入孔。

公开(公告)号：US20100013068A1

公开(公告)日：2010-01-21

申请号：US12208843

申请日：2008-09-11

Applicant: Han-Pei Huang ,  Chih-Peng Fan

Inventor： Han-Pei Huang ,  Chih-Peng Fan

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09518 ,  H05K2201/09809 ,  H01L2224/0401

Abstract: A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad.

Abstract translation: 公开了一种芯片封装载体，其包括第一电路层，第二电路层，芯层，第三电路层，第一和第三电路层之间的第一电介质层，第四导电层，至少包括焊球 垫，第二和第四电路层之间的第二电介质层和至少一个电容器器件，其中芯层至少具有第一通孔; 所述第三电路层设置在所述第一电路层上方，并且至少包括管芯焊盘; 电容器装置设置在第一通孔中。 本发明的电容器件包括覆盖第一通孔的壁的第一柱状电极，设置在第一柱状电极中并具有第一盲孔的圆筒形电容器材料和设置在第一盲孔中的第二柱状电极， 芯片垫。

公开(公告)号：US20080121417A1

公开(公告)日：2008-05-29

申请号：US11623553

申请日：2007-01-16

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer. The embedded capacitor is embedded in the first core circuit board and connected to the metal layer. A wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer. The dielectric layer is laminated between the first and the second core circuit boards.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括第一核心电路板，至少一个嵌入式电容器，第二核心电路板和电介质层。 至少一个金属层设置在第一芯电路板的表面上，并且第一芯电路板的至少一个第一导电通孔连接到金属层。 嵌入式电容器嵌入第一个核心电路板并连接到金属层。 布线层设置在第二芯电路板的表面上，并且第二芯电路板的至少一个第二导电通孔连接到布线层。 介电层层叠在第一和第二核心电路板之间。

公开(公告)号：US08289725B2

公开(公告)日：2012-10-16

申请号：US12851795

申请日：2010-08-06

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括芯电路板，至少一个电介质层，至少一个嵌入式电容器和至少一个金属层。 核心电路板具有至少一个布线层，并且核心电路板具有连接到布线层的至少一个导电通孔。 至少一个电介质层覆盖布线层，电介质层具有至少一个导电通孔。 至少一个嵌入式电容器嵌入电介质层。 至少一个金属层覆盖电介质层并连接到嵌入式电容器，其中金属层通过导电通孔连接到布线层。

公开(公告)号：US08186049B2

公开(公告)日：2012-05-29

申请号：US12181556

申请日：2008-07-29

Applicant: Chih-Peng Fan ,  Yen-Ti Chia

Inventor： Chih-Peng Fan ,  Yen-Ti Chia

IPC: H05K3/02

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.

Abstract translation: 电路结构的制造方法如下所述。 首先，在载体板上形成基底导电层，在基底导电层上形成具有至少一个露出基底导电层的一部分的沟槽的第一图案化电镀层。 然后在沟槽中形成第一图案化导电层，并且形成覆盖第一图案化导电层的一部分和第一图案化电镀层的一部分的第二图案化电镀层。 在暴露的第一图案化导电层上形成第二图案化导电层。 去除第一和第二图案化电镀层和由第一图案化导电层暴露的基底导电层。 然后，形成图案化的焊料掩模以覆盖第一图案化导电层的一部分。

公开(公告)号：US07906200B2

公开(公告)日：2011-03-15

申请号：US12424057

申请日：2009-04-15

Applicant: Tzyy-Jang Tseng ,  Chih-Peng Fan

Inventor： Tzyy-Jang Tseng ,  Chih-Peng Fan

IPC: B32B9/00

CPC classification number: H05K3/045 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/029 ,  H05K2203/0723 ,  H05K2203/107 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure.

Abstract translation: 复合电路基板结构包括第一电介质层，第二电介质层，玻璃纤维结构和图案化电路。 第一介电层具有彼此相对的第一表面和第二表面。 第二电介质层设置在第一电介质层上并且完全连接到第一表面。 玻璃纤维结构分布在第二电介质层中。 图案化电路从第二表面嵌入第一电介质层中，并且图案化电路不与玻璃纤维结构接触。

公开(公告)号：US20050098262A1

公开(公告)日：2005-05-12

申请号：US11015273

申请日：2004-12-16

Applicant: Chia-Pin Lin ,  Chih-Peng Fan ,  Chang-Yun Hung ,  Sheng-Chou Lee

Inventor： Chia-Pin Lin ,  Chih-Peng Fan ,  Chang-Yun Hung ,  Sheng-Chou Lee

IPC: B32B15/04 ,  B32B15/20 ,  H05K3/38 ,  B32B31/26

CPC classification number: B32B15/04 ,  B32B15/20 ,  B32B2037/243 ,  B32B2038/0076 ,  B32B2307/3065 ,  B32B2311/12 ,  B32B2379/08 ,  B32B2457/08 ,  H05K3/386 ,  H05K2201/0355 ,  H05K2203/0143 ,  H05K2203/0759 ,  H05K2203/1366

Abstract: A method of laminating copper foil onto a substrate of a printed circuit board, wherein the substrate has an upper surface and a lower surface. Isolating material is coated onto both surfaces of the substrate to form isolating layers on the substrate. The isolating layers can be formed by roll coating, spray coating or screen printing. The thickness of the isolating layers can be controlled in accordance to the requirements of the circuits. Various types of metal foils can be laminated onto the isolating layers, followed by heating and pressurization processes to secure the metal foil onto the substrate.

Abstract translation: 一种将铜箔层压到印刷电路板的基板上的方法，其中基板具有上表面和下表面。 将隔离材料涂覆在基板的两个表面上以在基板上形成隔离层。 隔离层可以通过辊涂，喷涂或丝网印刷形成。 隔离层的厚度可以根据电路的要求进行控制。 可以将各种类型的金属箔层压到隔离层上，然后进行加热和加压工艺以将金属箔固定到基底上。

公开(公告)号：US06395633B1

公开(公告)日：2002-05-28

申请号：US09871206

申请日：2001-05-31

Applicant: Jao-Chin Cheng ,  Chang-Chin Hsieh ,  Chih-Peng Fan ,  Chin-Chung Chang

Inventor： Jao-Chin Cheng ,  Chang-Chin Hsieh ,  Chih-Peng Fan ,  Chin-Chung Chang

IPC: H01L2144

CPC classification number: H05K3/4647 ,  H05K3/108 ,  H05K3/243 ,  H05K2203/0542 ,  H05K2203/0733

Abstract: A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.

Abstract translation: 一种形成微通孔的方法，用于制造和设计电路板的布局。 在基板上形成有图案的导电布线层。 将铜层镀在基板和导电布线层上。 在铜层上形成光致抗蚀剂层。 去除光致抗蚀剂层的一部分以露出铜层的一部分。 使用铜层作为种子层，在铜层的露出部分上形成导电柱。 去除光致抗蚀剂层。 暴露的镀铜层被去除。 在基板和导电柱的表面上形成绝缘层。 去除绝缘层的一部分以露出导电柱。 在导电柱上形成有图案的导电布线层。

公开(公告)号：US06343304B1

公开(公告)日：2002-01-29

申请号：US09265102

申请日：1999-03-09

Applicant: Jar-Ferr Yang ,  Chih-Peng Fan

Inventor： Jar-Ferr Yang ,  Chih-Peng Fan

IPC: G06F1714

CPC classification number: G06F17/147

Abstract: An apparatus with new fixed-coefficient recursive structures for computing discrete cosine transforms with the power-of-two length is disclosed. The fixed-coefficient recursive structures are developed from exploration of periodicity embedded in transform bases, whose indices can form a complete residue system or a complete odd residue system. Distinctively, we found that properly selected fixed-coefficient filters achieve lower round-off errors than the nominal variable-coefficient ones for computing DCTs in finite-word-length machines.

Abstract translation: 公开了一种具有新的固定系数递归结构的装置，用于计算功率为二的长度的离散余弦变换。 固定系数递归结构是从嵌入转化基期的周期性探索开发出来的，其指数可以形成完整的残留系统或完整的奇数残留系统。 特别地，我们发现，适当选择的固定系数滤波器实现比用于计算有限字长度机器中的DCT的标称可变系数滤波器更低的舍入误差。

公开(公告)号：US20130029500A1

公开(公告)日：2013-01-31

申请号：US13450485

申请日：2012-04-19

Applicant: Chih-Peng Fan ,  Ling-Kai Su ,  Yen-Ti Chia

Inventor： Chih-Peng Fan ,  Ling-Kai Su ,  Yen-Ti Chia

IPC: H01R12/71 ,  H01R43/16

CPC classification number: H01R13/24 ,  H01R4/04 ,  H01R43/16 ,  H01R43/20 ,  Y10T29/49224

Abstract: The present invention provides a connector including a substrate, at least a conductive via disposed inside the substrate, a pad disposed on one surface of the substrate and electrically connected to the conductive via, a resilient flange disposed on the pad, and an anisotropic conductive adhesive interposed between the pad and the resilient flange to electrically connect the pad with the resilient flange.

Abstract translation: 本发明提供了一种连接器，其包括基板，至少设置在基板内部的导电通孔，设置在基板的一个表面上并电连接到导电通孔的焊盘，设置在焊盘上的弹性凸缘和各向异性导电粘合剂 插入垫和弹性凸缘之间以将垫与弹性凸缘电连接。